From Newsgroup: sci.physics
Hi,
The word Musings has a totally new meaning:
Torbj||rn Lager wrote:
When
call(Goal), Self ! Pid-Goal
succeeds, that top-level goal has completed
and the actor terminates successfully.
Ok, I see. I thought it will be automatically
redone, and thus rapid fire multiple solutions.
So you have already hardwired a once/1 semantic
into your spawn/3, in that the spawn/3 goal argument
when executed, is onced, only looking at its EXIT
and FAIL port, not calling once more its REDO port.
This also means that both parallel/1 and
first_solution/1 have a short-cut AND
respective OR semantic:
/* AND-parallelism with short-cut */
parallel([G1,..,Gn]) <=> once(G1), .., once(G2)
/* OR-parallelism with short-cut */
first_solution([G1,..,Gn]) <=> once(G1); ..; once(G2)
The short-cut is in that parallel/1 can stop
at the first failure, and that first_solution/1
can stop at the first success. I wonder whether
Web Prolog Trinity offers true AND-parallelism or
true OR-parallelism without a short-cut. Having
such constructs could be interesting for problem
solving and is often used parallel search. For
example SICStus Prolog offers, or offered, true
OR-parallelism in its Multi-sequential Prolog
engines (Muse) extension, from the SICS experiments
in the 1990s with the BNN Butterfly supercomputer
from the 1980s:
yes
| ?- muse_flag(num_workers,_,5).
| ?- run.
724 solutions in 2.760 seconds.
yes
| ?- muse_flag(num_workers,_,1).
| ?- run.
724 solutions in 10.400 seconds.
https://sicstus.sics.se/sicstus/docs/3.7.1/html/sicstus_6.html
The intervention for true OR-paralleism is usually
at rule choice points. So when you have a set
of rules, like for example in the case of
the select/3 predicate:
select([X|Xs], Xs, X).
select([Y|Ys], [Y|Zs], X) :- select(Ys, Zs, X).
You execute it as:
select(X, Y, Z) :-
muse([select1(X,Y,Z), select2(X,Y,Z)]).
select1([X|Xs], Xs, X).
select2([Y|Ys], [Y|Zs], X) :- select(Ys, Zs, X).
Where the muse meta predicate has true OR parallelism:
muse([G1,..,Gn]) <=> G1 | .. | Gn
Bye
See also:
The muse approach to Or-parallel prolog
https://link.springer.com/article/10.1007/BF01407834
BBN Butterfly
https://en.wikipedia.org/wiki/BBN_Butterfly
P.S.: Maybe this explains my Freundlian slip when
I expected your parallel/1 to be some OR-parallelism,
while it is some AND-parallism. The true OR-parallelism
can be mathematically formalized in logic via
non-determinism and -C-calculus:
-C-calculus
https://ncatlab.org/nlab/show/pi-calculus
You even donrCOt need actor mailboxes, only channel objects.
Mild Shock schrieb:
Hi,
We recently implemented a parallel -C-WAM
on a GPU backend and could demonstrate an
estimated 11.4 Giga Lips. In this post we
report a further experiment, this time
presenting a parallel -C-WAM on a CPU backend,
that can lift specialized Prolog, currently
to 1.7 Giga Lips performance.
Having an excess number of threads is a
bad idea. What if we do context switching
on our own? With this approach we could
bring down the execution time of 128 Hack
VMs by 33%. We estimate for the test which
had 11.4 GLips on the GPU, that we reach
1.7 GLips on the CPU.
Bye
See also:
Parallel -C-WAM: 1.7 Giga Lips on a CPU
https://medium.com/2989/8a984e75af44
Mild Shock schrieb:
Hi,
TSMC's 2nm (N2) node and the 7 GHz target
represent a monumental milestone in silicon
manufacturing, shifting away from legacy
FinFETs to advanced Gate-All-Around (GAA)
nanosheet transistors.
This evolution allows chip designersrCoparticularly
in the PC and AI sectorsrCoto push processor
clock speeds previously thought impossible
on standard nodes
AMD confirms Zen 6 rollout for its July 22 AI event
https://videocardz.com/newz/amd-confirms-zen-6-launches-in-less-than-two-weeks-starting-with-epyc-venice
Production of the 6th Gen EPYC family is
already ramping up. AMD says Venice is its
first high-performance computing product
manufactured using TSMCrCOs 2nm process
technology.
Bye
Mild Shock schrieb:
Hi,
For marketing purposes people
typically look at the race towards
2nm, and we find:
A month ago, Apple lost its exclusivity
on 3 nm smartphone processors with
MediaTekrCOs Dimensity 9400 chip, integrated
in the Vivo X200 Pro smartphone. Qualcomm
is also in the race with its recently
unveiled Snapdragon 8 Elite and set to
power the Xiaomi 15 Pro in 2025. However,
Apple should regain its position as innovation
leader in 2026 with the release of the
iPhone 18, which should feature the A20
chip built on TSMCrCOs 2 nm process."
But there is a vertical vias revolution
going on as well, some SOCs typically
being at 18 layers now:
Zooming Into a CPU (It's Incredible)
https://www.youtube.com/watch?v=Bez-2cvYja0
imec has coined the term CMOS 2.0:
LEUVEN (Belgium), MARCH 12th, 2026 rCo Imec,
a world-leading research and innovation hub
in advanced semiconductor technologies, has
launched a first-of-its-kind consortium with
26 European university groups that will jointly
work on the technology roadmap beyond
CMOS scaling (CMOS 2.0).
https://www.imec-int.com/en/press/imec-launches-university-consortium-around-next-generation-chips
So we might see more mobile grade GPUs.
Bye
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