john larkin <jl@glen--canyon.com>wrote:
Take a look at the data sheet
https://www.digikey.com/en/products/detail/infineon-technologies/IPD180N10N3GATMA1/6599595
specifically fig 3, the SOAR curve.
The "limited by on-state resistance" line is about 40 mohms, but the
typical Rds-on value is 15.
The 10 millisecond line hits 1 amp and 30 volts, which is 30 watts.
But the part is rated for 71 watts.
I wonder what D = 0 means.
I guess I'll blow some up and see what they can really do.
Take a look at the data sheet
https://www.digikey.com/en/products/detail/infineon-technologies/IPD180N10N3GATMA1/6599595
specifically fig 3, the SOAR curve.
The "limited by on-state resistance" line is about 40 mohms, but the
typical Rds-on value is 15.
The 10 millisecond line hits 1 amp and 30 volts, which is 30 watts.
But the part is rated for 71 watts.
I wonder what D = 0 means.
I guess I'll blow some up and see what they can really do.
Un bel giorno john larkin digit>:
Take a look at the data sheet
https://www.digikey.com/en/products/detail/infineon-technologies/IPD180N10N3GATMA1/6599595
specifically fig 3, the SOAR curve.
The "limited by on-state resistance" line is about 40 mohms, but the
typical Rds-on value is 15.
The 10 millisecond line hits 1 amp and 30 volts, which is 30 watts.
But the part is rated for 71 watts.
I wonder what D = 0 means.
I guess I'll blow some up and see what they can really do.
I would say that the SOA figure shows you the "worst case" data, therefore >they consider the maximum Rds(on) instead of the typical. D=0 means a
single pulse (no duty cycle).
The part is rated for 71W when it is completely ON; they don't say it >explicitly, but for switching MOSFETs it is implied. Instead, with Vds=30V >and 1A you are in the linear region, and the power is limited also by other >factors than "just" the joule effect (e.g. thermal runaway, second >breakdown). If you follow the same 10 ms curve up to the Rds(on) limit,
where the MOSFET is completely ON, you have about 2V, 50A which is 100W: as >expected the peak power is greater with shorter pulses (see also the figure >4).
There are specific MOSFET families made to be used in the linear region,
that have a wider SOA. However MOSFETs are always less happy to be used in >the linear region than bipolar transistors.
Take a look at the data sheet
https://www.digikey.com/en/products/detail/infineon-technologies/IPD180N10N3GATMA1/6599595
specifically fig 3, the SOAR curve.
The "limited by on-state resistance" line is about 40 mohms, but the
typical Rds-on value is 15.
Take a look at the data sheet
https://www.digikey.com/en/products/detail/infineon-technologies/IPD180N10N3GATMA1/6599595
specifically fig 3, the SOAR curve.
The "limited by on-state resistance" line is about 40 mohms, but the
typical Rds-on value is 15.
The 10 millisecond line hits 1 amp and 30 volts, which is 30 watts.
But the part is rated for 71 watts.
I wonder what D = 0 means.
I guess I'll blow some up and see what they can really do.
john larkin <jl@glen--canyon.com> wrote:
Take a look at the data sheet
https://www.digikey.com/en/products/detail/infineon-technologies/IPD180N10N3GATMA1/6599595
specifically fig 3, the SOAR curve.
The "limited by on-state resistance" line is about 40 mohms, but the
typical Rds-on value is 15.
Typical is usually at room temperature. SOA curve probably uses
maximal possible Rds-on which is likely to be at higher temperature.
IIUC actual SOA may be larger, but they do not want to draw too
complex boundaries.
On Mon, 22 Jun 2026 01:27:15 -0000 (UTC), antispam@fricas.org (Waldek Hebisch) wrote:
john larkin <jl@glen--canyon.com> wrote:
Take a look at the data sheet
https://www.digikey.com/en/products/detail/infineon-technologies/IPD180N10N3GATMA1/6599595
specifically fig 3, the SOAR curve.
The "limited by on-state resistance" line is about 40 mohms, but the
typical Rds-on value is 15.
Typical is usually at room temperature. SOA curve probably uses
maximal possible Rds-on which is likely to be at higher temperature.
IIUC actual SOA may be larger, but they do not want to draw too
complex boundaries.
That doesn't explain it. Rds-on max is 18 mohms, and the SOAR graph
says 25 deg C.
SOAR curves must be assigned to the dullest interns.
On 22/06/2026 11:51 pm, john larkin wrote:
On Mon, 22 Jun 2026 01:27:15 -0000 (UTC), antispam@fricas.org (Waldek
Hebisch) wrote:
john larkin <jl@glen--canyon.com> wrote:
Take a look at the data sheet
https://www.digikey.com/en/products/detail/infineon-technologies/IPD180N10N3GATMA1/6599595
specifically fig 3, the SOAR curve.
The "limited by on-state resistance" line is about 40 mohms, but the
typical Rds-on value is 15.
Typical is usually at room temperature. SOA curve probably uses
maximal possible Rds-on which is likely to be at higher temperature.
IIUC actual SOA may be larger, but they do not want to draw too
complex boundaries.
That doesn't explain it. Rds-on max is 18 mohms, and the SOAR graph
says 25 deg C.
The external temperature may be 25 degrees Celcius, but temperature that >matters is in the middle of the die.
Dissipate enough heat in the channel - 33A across 0.04R is 44W or about
90C of temperature rise in the channel, which brings the Rds-on closer
to 0.04R
SOAR curves must be assigned to the dullest interns.
Sometimes they get read by decidedly dull engineers.
On Sun, 21 Jun 2026 08:03:16 -0700, john larkin <jl@glen--canyon.com>
wrote:
Take a look at the data sheet
https://www.digikey.com/en/products/detail/infineon-technologies/IPD180N10N3GATMA1/6599595
specifically fig 3, the SOAR curve.
The "limited by on-state resistance" line is about 40 mohms, but the >>typical Rds-on value is 15.
The part is specified for RDSon>=33mR at VGS=6V.
The 10 millisecond line hits 1 amp and 30 volts, which is 30 watts.
But the part is rated for 71 watts.
I wonder what D = 0 means.
Single pulde.
You'd need a measurement for Tj - this ain't gonna happen.
I guess I'll blow some up and see what they can really do.
If melted wafer solder floats your boat, then go ahead.
RL
On Tue, 23 Jun 2026 00:14:04 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 22/06/2026 11:51 pm, john larkin wrote:
On Mon, 22 Jun 2026 01:27:15 -0000 (UTC), antispam@fricas.org (Waldek
Hebisch) wrote:
john larkin <jl@glen--canyon.com> wrote:
Take a look at the data sheet
https://www.digikey.com/en/products/detail/infineon-technologies/IPD180N10N3GATMA1/6599595
specifically fig 3, the SOAR curve.
The "limited by on-state resistance" line is about 40 mohms, but the >>>>> typical Rds-on value is 15.
Typical is usually at room temperature. SOA curve probably uses
maximal possible Rds-on which is likely to be at higher temperature.
IIUC actual SOA may be larger, but they do not want to draw too
complex boundaries.
That doesn't explain it. Rds-on max is 18 mohms, and the SOAR graph
says 25 deg C.
The external temperature may be 25 degrees Celcius, but temperature that
matters is in the middle of the die.
Dissipate enough heat in the channel - 33A across 0.04R is 44W or about
90C of temperature rise in the channel, which brings the Rds-on closer
to 0.04R
SOAR curves must be assigned to the dullest interns.
Sometimes they get read by decidedly dull engineers.
The "limited by on resistance" is a straight line, always 40 mohms.
Explain that.
On Mon, 22 Jun 2026 09:46:33 -0400, legg <legg@nospam.magma.ca> wrote:
On Sun, 21 Jun 2026 08:03:16 -0700, john larkin <jl@glen--canyon.com>
wrote:
Take a look at the data sheet
https://www.digikey.com/en/products/detail/infineon-technologies/IPD180N10N3GATMA1/6599595
specifically fig 3, the SOAR curve.
The "limited by on-state resistance" line is about 40 mohms, but the
typical Rds-on value is 15.
The part is specified for RDSon>=33mR at VGS=6V.
I wonder why they did the SOAR graph with 6 volts on the gate.
The 10 millisecond line hits 1 amp and 30 volts, which is 30 watts.
But the part is rated for 71 watts.
I wonder what D = 0 means.
Single pulse.
You'd need a measurement for Tj - this ain't gonna happen.
I guess I'll blow some up and see what they can really do.
If melted wafer solder floats your boat, then go ahead.
We just need to figure out what kills them, and back off some.
We did that for our NMR gradient driver fets.
https://www.dropbox.com/scl/fi/oq1bgzkpsdcsmrg63w1r9/ExFets.jpg?rlkey=jcscvg5vt1qebgyxb0gt5575q&raw=1
The SOAR curves were no help.
On 23/06/2026 1:12 am, john larkin wrote:
On Tue, 23 Jun 2026 00:14:04 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 22/06/2026 11:51 pm, john larkin wrote:
On Mon, 22 Jun 2026 01:27:15 -0000 (UTC), antispam@fricas.org (Waldek
Hebisch) wrote:
john larkin <jl@glen--canyon.com> wrote:
Take a look at the data sheet
https://www.digikey.com/en/products/detail/infineon-technologies/IPD180N10N3GATMA1/6599595
specifically fig 3, the SOAR curve.
The "limited by on-state resistance" line is about 40 mohms, but the >>>>>> typical Rds-on value is 15.
Typical is usually at room temperature. SOA curve probably uses
maximal possible Rds-on which is likely to be at higher temperature. >>>>> IIUC actual SOA may be larger, but they do not want to draw too
complex boundaries.
That doesn't explain it. Rds-on max is 18 mohms, and the SOAR graph
says 25 deg C.
The external temperature may be 25 degrees Celcius, but temperature that >>> matters is in the middle of the die.
Dissipate enough heat in the channel - 33A across 0.04R is 44W or about
90C of temperature rise in the channel, which brings the Rds-on closer
to 0.04R
SOAR curves must be assigned to the dullest interns.
Sometimes they get read by decidedly dull engineers.
The "limited by on resistance" is a straight line, always 40 mohms.
Explain that.
It's an example of what a constant 40mOhm resistance would do. What did
you think it meant?
On Tue, 23 Jun 2026 12:34:11 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 23/06/2026 1:12 am, john larkin wrote:
On Tue, 23 Jun 2026 00:14:04 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 22/06/2026 11:51 pm, john larkin wrote:
On Mon, 22 Jun 2026 01:27:15 -0000 (UTC), antispam@fricas.org (Waldek >>>>> Hebisch) wrote:
john larkin <jl@glen--canyon.com> wrote:
Take a look at the data sheet
https://www.digikey.com/en/products/detail/infineon-technologies/IPD180N10N3GATMA1/6599595
specifically fig 3, the SOAR curve.
The "limited by on-state resistance" line is about 40 mohms, but the >>>>>>> typical Rds-on value is 15.
Typical is usually at room temperature. SOA curve probably uses
maximal possible Rds-on which is likely to be at higher temperature. >>>>>> IIUC actual SOA may be larger, but they do not want to draw too
complex boundaries.
That doesn't explain it. Rds-on max is 18 mohms, and the SOAR graph
says 25 deg C.
The external temperature may be 25 degrees Celcius, but temperature that >>>> matters is in the middle of the die.
Dissipate enough heat in the channel - 33A across 0.04R is 44W or about >>>> 90C of temperature rise in the channel, which brings the Rds-on closer >>>> to 0.04R
SOAR curves must be assigned to the dullest interns.
Sometimes they get read by decidedly dull engineers.
The "limited by on resistance" is a straight line, always 40 mohms.
Explain that.
It's an example of what a constant 40mOhm resistance would do. What did
you think it meant?
I have no idea why they plotted 40 milliohms. The point where I plan
to operate is 50 amps and, probably, around 0.75 volts. According to
the SOAR graph, that doesn't even exist.
I just Dremel'd a test board, two fets to make 100 amp pulses. I'm
waiting for the fets to finish it. I'll pulse it for a month or so to
make sure things are stable.
Avtech suddenly went out of business and we have some inquiries. One
problem is that Avtech had a zillion products with a zillion variants,
so they didn't sell many of each.
I wonder why they did the SOAR graph with 6 volts on the gate.
John Larkin--- Synchronet 3.22a-Linux NewsLink 1.2
Highland Tech Glen Canyon Design Center
Lunatic Fringe Electronics
john larkin <jl@glen--canyon.com> wrote:
On Tue, 23 Jun 2026 12:34:11 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 23/06/2026 1:12 am, john larkin wrote:
On Tue, 23 Jun 2026 00:14:04 +1000, Bill Sloman <bill.sloman@ieee.org> >>>> wrote:
On 22/06/2026 11:51 pm, john larkin wrote:
On Mon, 22 Jun 2026 01:27:15 -0000 (UTC), antispam@fricas.org (Waldek >>>>>> Hebisch) wrote:
john larkin <jl@glen--canyon.com> wrote:
Take a look at the data sheet
https://www.digikey.com/en/products/detail/infineon-technologies/IPD180N10N3GATMA1/6599595
specifically fig 3, the SOAR curve.
The "limited by on-state resistance" line is about 40 mohms, but the >>>>>>>> typical Rds-on value is 15.
Typical is usually at room temperature. SOA curve probably uses >>>>>>> maximal possible Rds-on which is likely to be at higher temperature. >>>>>>> IIUC actual SOA may be larger, but they do not want to draw too
complex boundaries.
That doesn't explain it. Rds-on max is 18 mohms, and the SOAR graph >>>>>> says 25 deg C.
The external temperature may be 25 degrees Celcius, but temperature that >>>>> matters is in the middle of the die.
Dissipate enough heat in the channel - 33A across 0.04R is 44W or about >>>>> 90C of temperature rise in the channel, which brings the Rds-on closer >>>>> to 0.04R
SOAR curves must be assigned to the dullest interns.
Sometimes they get read by decidedly dull engineers.
The "limited by on resistance" is a straight line, always 40 mohms.
Explain that.
It's an example of what a constant 40mOhm resistance would do. What did
you think it meant?
I have no idea why they plotted 40 milliohms. The point where I plan
to operate is 50 amps and, probably, around 0.75 volts. According to
the SOAR graph, that doesn't even exist.
I just Dremel'd a test board, two fets to make 100 amp pulses. I'm
waiting for the fets to finish it. I'll pulse it for a month or so to
make sure things are stable.
Avtech suddenly went out of business and we have some inquiries. One
problem is that Avtech had a zillion products with a zillion variants,
so they didn't sell many of each.
Fun. They made some cool stuff.
john larkin <jl@glen--canyon.com> wrote:
On Tue, 23 Jun 2026 12:34:11 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 23/06/2026 1:12 am, john larkin wrote:
On Tue, 23 Jun 2026 00:14:04 +1000, Bill Sloman <bill.sloman@ieee.org> >>>> wrote:
On 22/06/2026 11:51 pm, john larkin wrote:
On Mon, 22 Jun 2026 01:27:15 -0000 (UTC), antispam@fricas.org (Waldek >>>>>> Hebisch) wrote:
john larkin <jl@glen--canyon.com> wrote:
Take a look at the data sheet
https://www.digikey.com/en/products/detail/infineon-technologies/IPD180N10N3GATMA1/6599595
specifically fig 3, the SOAR curve.
The "limited by on-state resistance" line is about 40 mohms, but the >>>>>>>> typical Rds-on value is 15.
Typical is usually at room temperature. SOA curve probably uses >>>>>>> maximal possible Rds-on which is likely to be at higher temperature. >>>>>>> IIUC actual SOA may be larger, but they do not want to draw too
complex boundaries.
That doesn't explain it. Rds-on max is 18 mohms, and the SOAR graph >>>>>> says 25 deg C.
The external temperature may be 25 degrees Celcius, but temperature that >>>>> matters is in the middle of the die.
Dissipate enough heat in the channel - 33A across 0.04R is 44W or about >>>>> 90C of temperature rise in the channel, which brings the Rds-on closer >>>>> to 0.04R
SOAR curves must be assigned to the dullest interns.
Sometimes they get read by decidedly dull engineers.
The "limited by on resistance" is a straight line, always 40 mohms.
Explain that.
It's an example of what a constant 40mOhm resistance would do. What did >>> you think it meant?
I have no idea why they plotted 40 milliohms. The point where I plan
to operate is 50 amps and, probably, around 0.75 volts. According to
the SOAR graph, that doesn't even exist.
I just Dremel'd a test board, two fets to make 100 amp pulses. I'm
waiting for the fets to finish it. I'll pulse it for a month or so to
make sure things are stable.
Avtech suddenly went out of business and we have some inquiries. One
problem is that Avtech had a zillion products with a zillion variants,
so they didn't sell many of each.
Fun. They made some cool stuff.
Cheers
Phil Hobbs
On Tue, 23 Jun 2026 03:26:39 -0000 (UTC), Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:
john larkin <jl@glen--canyon.com> wrote:
On Tue, 23 Jun 2026 12:34:11 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 23/06/2026 1:12 am, john larkin wrote:
On Tue, 23 Jun 2026 00:14:04 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>> wrote:
On 22/06/2026 11:51 pm, john larkin wrote:
On Mon, 22 Jun 2026 01:27:15 -0000 (UTC), antispam@fricas.org (Waldek >>>>>>> Hebisch) wrote:
john larkin <jl@glen--canyon.com> wrote:
Take a look at the data sheet
https://www.digikey.com/en/products/detail/infineon-technologies/IPD180N10N3GATMA1/6599595
specifically fig 3, the SOAR curve.
The "limited by on-state resistance" line is about 40 mohms, but the >>>>>>>>> typical Rds-on value is 15.
Typical is usually at room temperature. SOA curve probably uses >>>>>>>> maximal possible Rds-on which is likely to be at higher temperature. >>>>>>>> IIUC actual SOA may be larger, but they do not want to draw too >>>>>>>> complex boundaries.
That doesn't explain it. Rds-on max is 18 mohms, and the SOAR graph >>>>>>> says 25 deg C.
The external temperature may be 25 degrees Celcius, but temperature that >>>>>> matters is in the middle of the die.
Dissipate enough heat in the channel - 33A across 0.04R is 44W or about >>>>>> 90C of temperature rise in the channel, which brings the Rds-on closer >>>>>> to 0.04R
SOAR curves must be assigned to the dullest interns.
Sometimes they get read by decidedly dull engineers.
The "limited by on resistance" is a straight line, always 40 mohms.
Explain that.
It's an example of what a constant 40mOhm resistance would do. What did >>>> you think it meant?
I have no idea why they plotted 40 milliohms. The point where I plan
to operate is 50 amps and, probably, around 0.75 volts. According to
the SOAR graph, that doesn't even exist.
I just Dremel'd a test board, two fets to make 100 amp pulses. I'm
waiting for the fets to finish it. I'll pulse it for a month or so to
make sure things are stable.
Avtech suddenly went out of business and we have some inquiries. One
problem is that Avtech had a zillion products with a zillion variants,
so they didn't sell many of each.
Fun. They made some cool stuff.
Cheers
Phil Hobbs
It semed to be a sort of hobby business for the founder. Lots of
complex stuff full of avalanche transistors, varicaps, SRDs, DSRDs,
SiC fets, transmission lines. Yes, fun stuff.
https://www.dropbox.com/scl/fi/2uqqmt4ag4up7jsl7u7yu/s-l1600-1.jpg?rlkey=udsbfvyp2bzzpgfkyvtv58eyy&raw=1
But not very manufacturable. When he died, his son, an MD, didn't want
to keep it going.
https://www.avtechpulse.com/
We were surprised to find ourselves listed as a possible replacement.
john larkin <jl@glen--canyon.com> wrote:
On Tue, 23 Jun 2026 03:26:39 -0000 (UTC), Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:
john larkin <jl@glen--canyon.com> wrote:
On Tue, 23 Jun 2026 12:34:11 +1000, Bill Sloman <bill.sloman@ieee.org> >>>> wrote:
On 23/06/2026 1:12 am, john larkin wrote:
On Tue, 23 Jun 2026 00:14:04 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>> wrote:
On 22/06/2026 11:51 pm, john larkin wrote:
On Mon, 22 Jun 2026 01:27:15 -0000 (UTC), antispam@fricas.org (Waldek >>>>>>>> Hebisch) wrote:
john larkin <jl@glen--canyon.com> wrote:
Take a look at the data sheet
https://www.digikey.com/en/products/detail/infineon-technologies/IPD180N10N3GATMA1/6599595
specifically fig 3, the SOAR curve.
The "limited by on-state resistance" line is about 40 mohms, but the >>>>>>>>>> typical Rds-on value is 15.
Typical is usually at room temperature. SOA curve probably uses >>>>>>>>> maximal possible Rds-on which is likely to be at higher temperature. >>>>>>>>> IIUC actual SOA may be larger, but they do not want to draw too >>>>>>>>> complex boundaries.
That doesn't explain it. Rds-on max is 18 mohms, and the SOAR graph >>>>>>>> says 25 deg C.
The external temperature may be 25 degrees Celcius, but temperature that
matters is in the middle of the die.
Dissipate enough heat in the channel - 33A across 0.04R is 44W or about >>>>>>> 90C of temperature rise in the channel, which brings the Rds-on closer >>>>>>> to 0.04R
SOAR curves must be assigned to the dullest interns.
Sometimes they get read by decidedly dull engineers.
The "limited by on resistance" is a straight line, always 40 mohms. >>>>>>
Explain that.
It's an example of what a constant 40mOhm resistance would do. What did >>>>> you think it meant?
I have no idea why they plotted 40 milliohms. The point where I plan
to operate is 50 amps and, probably, around 0.75 volts. According to
the SOAR graph, that doesn't even exist.
I just Dremel'd a test board, two fets to make 100 amp pulses. I'm
waiting for the fets to finish it. I'll pulse it for a month or so to
make sure things are stable.
Avtech suddenly went out of business and we have some inquiries. One
problem is that Avtech had a zillion products with a zillion variants, >>>> so they didn't sell many of each.
Fun. They made some cool stuff.
Cheers
Phil Hobbs
It semed to be a sort of hobby business for the founder. Lots of
complex stuff full of avalanche transistors, varicaps, SRDs, DSRDs,
SiC fets, transmission lines. Yes, fun stuff.
https://www.dropbox.com/scl/fi/2uqqmt4ag4up7jsl7u7yu/s-l1600-1.jpg?rlkey=udsbfvyp2bzzpgfkyvtv58eyy&raw=1
But not very manufacturable. When he died, his son, an MD, didn't want
to keep it going.
https://www.avtechpulse.com/
We were surprised to find ourselves listed as a possible replacement.
We might be interested in doing some of that stuff too.
Cheers
Phil Hobbs
On Tue, 23 Jun 2026 17:19:02 -0000 (UTC), Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:
john larkin <jl@glen--canyon.com> wrote:
On Tue, 23 Jun 2026 03:26:39 -0000 (UTC), Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:
john larkin <jl@glen--canyon.com> wrote:
On Tue, 23 Jun 2026 12:34:11 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>> wrote:
On 23/06/2026 1:12 am, john larkin wrote:
On Tue, 23 Jun 2026 00:14:04 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>>> wrote:
On 22/06/2026 11:51 pm, john larkin wrote:
On Mon, 22 Jun 2026 01:27:15 -0000 (UTC), antispam@fricas.org (Waldek >>>>>>>>> Hebisch) wrote:
john larkin <jl@glen--canyon.com> wrote:
Avtech suddenly went out of business and we have some inquiries. One >>>>> problem is that Avtech had a zillion products with a zillion variants, >>>>> so they didn't sell many of each.
Fun. They made some cool stuff.
Cheers
It semed to be a sort of hobby business for the founder. Lots of
complex stuff full of avalanche transistors, varicaps, SRDs, DSRDs,
SiC fets, transmission lines. Yes, fun stuff.
https://www.dropbox.com/scl/fi/2uqqmt4ag4up7jsl7u7yu/s-l1600-1.jpg?rlkey=udsbfvyp2bzzpgfkyvtv58eyy&raw=1
But not very manufacturable. When he died, his son, an MD, didn't want
to keep it going.
https://www.avtechpulse.com/
We were surprised to find ourselves listed as a possible replacement.
We might be interested in doing some of that stuff too.
We are! We are doing a 650 volt pulse generator and a 100 amp 100
volt laser driver. Both tiny blue boxes.
https://www.dropbox.com/scl/fi/ib7n9d2pp5ej6p7cr14ji/B250.jpg?rlkey=c8yo4370j8507proreryl85h6&raw=1
On Mon, 22 Jun 2026 08:17:41 -0700, john larkin <jl@glen--canyon.com>
wrote:
I wonder why they did the SOAR graph with 6 volts on the gate.
Where does it say they did? The headline Rds value is given at a Tj
of 25 C. The SOA graph is with the junction(s) at max working temp.
There is nothing wrong with the graph.
John Larkin
Highland Tech Glen Canyon Design Center
Lunatic Fringe Electronics
On Tue, 23 Jun 2026 05:57:12 +0100, JM
<sunaecoNoChoppedPork@gmail.com> wrote:
On Mon, 22 Jun 2026 08:17:41 -0700, john larkin <jl@glen--canyon.com> >>wrote:
I wonder why they did the SOAR graph with 6 volts on the gate.
Where does it say they did? The headline Rds value is given at a Tj
of 25 C. The SOA graph is with the junction(s) at max working temp.
There is nothing wrong with the graph.
John Larkin
Highland Tech Glen Canyon Design Center
Lunatic Fringe Electronics
The title of the SOAR graph clearly says Tc=25c.
Rds-on is typ 15 mohms, as shown in fig 6. The "limited by on-state
resistance" line is 40m all the way from 0.25 watts to 1 KW.
I'll just blow some up and see what they actually do.
John Larkin--- Synchronet 3.22a-Linux NewsLink 1.2
Highland Tech Glen Canyon Design Center
Lunatic Fringe Electronics
On Tue, 23 Jun 2026 05:57:12 +0100, JM
<sunaecoNoChoppedPork@gmail.com> wrote:
On Mon, 22 Jun 2026 08:17:41 -0700, john larkin <jl@glen--canyon.com>
wrote:
I wonder why they did the SOAR graph with 6 volts on the gate.
Where does it say they did? The headline Rds value is given at a Tj
of 25 C. The SOA graph is with the junction(s) at max working temp.
There is nothing wrong with the graph.
The title of the SOAR graph clearly says Tc=25c.
Rds-on is typ 15 mohms, as shown in fig 6. The "limited by on-state resistance" line is 40m all the way from 0.25 watts to 1 KW.
I'll just blow some up and see what they actually do.
On Wed, 24 Jun 2026 07:17:18 -0700, john larkin <jl@glen--canyon.com>
wrote:
On Tue, 23 Jun 2026 05:57:12 +0100, JM
<sunaecoNoChoppedPork@gmail.com> wrote:
On Mon, 22 Jun 2026 08:17:41 -0700, john larkin <jl@glen--canyon.com> >>>wrote:
I wonder why they did the SOAR graph with 6 volts on the gate.
Where does it say they did? The headline Rds value is given at a Tj
of 25 C. The SOA graph is with the junction(s) at max working temp.
There is nothing wrong with the graph.
John Larkin
Highland Tech Glen Canyon Design Center
Lunatic Fringe Electronics
The title of the SOAR graph clearly says Tc=25c.
That is the case temperature. The whole point of the SOA graph is to
provide an indication of where parts of the die reach the maximum
operating temperature.
Rds-on is typ 15 mohms, as shown in fig 6. The "limited by on-state
At a die teperature of 25 C.
resistance" line is 40m all the way from 0.25 watts to 1 KW.
I'll just blow some up and see what they actually do.
And how do you think Infineon measure the SOA?
Read the thermal instability paper by Berglio and Spirito.
On Wed, 24 Jun 2026 15:27:09 +0100, JM
<sunaecoNoChoppedPork@gmail.com> wrote:
On Wed, 24 Jun 2026 07:17:18 -0700, john larkin <jl@glen--canyon.com>
wrote:
On Tue, 23 Jun 2026 05:57:12 +0100, JM
<sunaecoNoChoppedPork@gmail.com> wrote:
On Mon, 22 Jun 2026 08:17:41 -0700, john larkin <jl@glen--canyon.com>
wrote:
I wonder why they did the SOAR graph with 6 volts on the gate.
Where does it say they did? The headline Rds value is given at a Tj
of 25 C. The SOA graph is with the junction(s) at max working temp.
There is nothing wrong with the graph.
John Larkin
Highland Tech Glen Canyon Design Center
Lunatic Fringe Electronics
The title of the SOAR graph clearly says Tc=25c.
That is the case temperature. The whole point of the SOA graph is to
provide an indication of where parts of the die reach the maximum
operating temperature.
Rds-on is typ 15 mohms, as shown in fig 6. The "limited by on-state
At a die teperature of 25 C.
What do you expect the die temp to be at 25c case temp and 0.25 watts dissipation?
resistance" line is 40m all the way from 0.25 watts to 1 KW.
I'll just blow some up and see what they actually do.
And how do you think Infineon measure the SOA?
Read the thermal instability paper by Berglio and Spirito.
When we tested a lot of big fets for our NMR drivers, we developed a different thermal model. It worked fine.
Clamp mounted fets don't have a mounting screw hole, so there's more
room for silicon. Note: no insulators.
On 25/06/2026 1:37 am, john larkin wrote:
On Wed, 24 Jun 2026 15:27:09 +0100, JM
<sunaecoNoChoppedPork@gmail.com> wrote:
On Wed, 24 Jun 2026 07:17:18 -0700, john larkin <jl@glen--canyon.com>
wrote:
On Tue, 23 Jun 2026 05:57:12 +0100, JM
<sunaecoNoChoppedPork@gmail.com> wrote:
On Mon, 22 Jun 2026 08:17:41 -0700, john larkin <jl@glen--canyon.com> >>>>> wrote:
I wonder why they did the SOAR graph with 6 volts on the gate.
Where does it say they did? The headline Rds value is given at a Tj >>>>> of 25 C. The SOA graph is with the junction(s) at max working temp. >>>>>
There is nothing wrong with the graph.
John Larkin
Highland Tech Glen Canyon Design Center
Lunatic Fringe Electronics
The title of the SOAR graph clearly says Tc=25c.
That is the case temperature. The whole point of the SOA graph is to
provide an indication of where parts of the die reach the maximum
operating temperature.
Rds-on is typ 15 mohms, as shown in fig 6. The "limited by on-state
At a die teperature of 25 C.
What do you expect the die temp to be at 25c case temp and 0.25 watts
dissipation?
Read the data sheet.
resistance" line is 40m all the way from 0.25 watts to 1 KW.
I'll just blow some up and see what they actually do.
And how do you think Infineon measure the SOA?
Read the thermal instability paper by Berglio and Spirito.
When we tested a lot of big fets for our NMR drivers, we developed a
different thermal model. It worked fine.
Lots of different models work adequately.
<snipped uninformative advertising.>
Clamp mounted fets don't have a mounting screw hole, so there's more
room for silicon. Note: no insulators.
Why should we pay attention to the presence or absence of insulators?
Most FETs have lots of exposed metal so you can connect to gate, source
and drain. The gate connection doesn't have to carry a lot of current
except when the device is being turned on and off.
Insulators separate conductors that are carrying different currents, so
they are inevitable - your "Note: no insulators" is nonsense on the face
of it. You do need to learn to say what you mean, at least when you are >pretending to say something informative.
On 25/06/2026 12:17 am, john larkin wrote:
On Tue, 23 Jun 2026 05:57:12 +0100, JM
<sunaecoNoChoppedPork@gmail.com> wrote:
On Mon, 22 Jun 2026 08:17:41 -0700, john larkin <jl@glen--canyon.com>
wrote:
I wonder why they did the SOAR graph with 6 volts on the gate.
Where does it say they did? The headline Rds value is given at a Tj
of 25 C. The SOA graph is with the junction(s) at max working temp.
There is nothing wrong with the graph.
The title of the SOAR graph clearly says Tc=25c.
But that's the external temperature, not the temperature of the
conducting channel inside the device,
Rds-on is typ 15 mohms, as shown in fig 6. The "limited by on-state
resistance" line is 40m all the way from 0.25 watts to 1 KW.
Because the conducting channel gets warmer when it is carrying more
current. Resistance isn't supposed to be current dependent, but when
there's enough current going through the conductor to warm it up, the >temperature dependence of the resistance does come into play.
The channel resistance is not going to be a nice stable 40 mOhm at all >currents, but the application engineer seems to have decided that 40 >milliOhm was close enough
I'll just blow some up and see what they actually do.
Thinking about what's actually going on inside the devices as you blow
them up would let you get more information out of the exercise, but
might diminish the emotional gratification.
What do you expect the die temp to be at 25c case temp and 0.25 watts >dissipation?
I have no idea why they plotted 40 milliohms. The point where I plan
to operate is 50 amps and, probably, around 0.75 volts.
Take a look at the data sheet
https://www.digikey.com/en/products/detail/infineon-technologies/IPD180N10N3GATMA1/6599595
specifically fig 3, the SOAR curve.
The "limited by on-state resistance" line is about 40 mohms, but the
typical Rds-on value is 15.
The 10 millisecond line hits 1 amp and 30 volts, which is 30 watts.
But the part is rated for 71 watts.
I wonder what D = 0 means.
I guess I'll blow some up and see what they can really do.
John Larkin
Highland Tech Glen Canyon Design Center
Lunatic Fringe Electronics
On Thu, 25 Jun 2026 02:12:01 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 25/06/2026 1:37 am, john larkin wrote:
On Wed, 24 Jun 2026 15:27:09 +0100, JM
<sunaecoNoChoppedPork@gmail.com> wrote:
On Wed, 24 Jun 2026 07:17:18 -0700, john larkin <jl@glen--canyon.com>
wrote:
On Tue, 23 Jun 2026 05:57:12 +0100, JM
<sunaecoNoChoppedPork@gmail.com> wrote:
On Mon, 22 Jun 2026 08:17:41 -0700, john larkin <jl@glen--canyon.com> >>>>>> wrote:
I wonder why they did the SOAR graph with 6 volts on the gate.
Where does it say they did? The headline Rds value is given at a Tj >>>>>> of 25 C. The SOA graph is with the junction(s) at max working temp. >>>>>>
There is nothing wrong with the graph.
John Larkin
Highland Tech Glen Canyon Design Center
Lunatic Fringe Electronics
The title of the SOAR graph clearly says Tc=25c.
That is the case temperature. The whole point of the SOA graph is to
provide an indication of where parts of the die reach the maximum
operating temperature.
Rds-on is typ 15 mohms, as shown in fig 6. The "limited by on-state
At a die teperature of 25 C.
What do you expect the die temp to be at 25c case temp and 0.25 watts
dissipation?
Read the data sheet.
resistance" line is 40m all the way from 0.25 watts to 1 KW.
I'll just blow some up and see what they actually do.
And how do you think Infineon measure the SOA?
Read the thermal instability paper by Berglio and Spirito.
When we tested a lot of big fets for our NMR drivers, we developed a
different thermal model. It worked fine.
Lots of different models work adequately.
<snipped uninformative advertising.>
Clamp mounted fets don't have a mounting screw hole, so there's more
room for silicon. Note: no insulators.
Why should we pay attention to the presence or absence of insulators?
Most FETs have lots of exposed metal so you can connect to gate, source
and drain. The gate connection doesn't have to carry a lot of current
except when the device is being turned on and off.
Insulators separate conductors that are carrying different currents, so
they are inevitable - your "Note: no insulators" is nonsense on the face
of it. You do need to learn to say what you mean, at least when you are
pretending to say something informative.
The thermal resistance of the insulators on that amp is exactly zero.
The fets are clamped onto copper bars, which spread the heat into the aluminum heat sink.
On Thu, 25 Jun 2026 01:28:18 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 25/06/2026 12:17 am, john larkin wrote:
On Tue, 23 Jun 2026 05:57:12 +0100, JM
<sunaecoNoChoppedPork@gmail.com> wrote:
On Mon, 22 Jun 2026 08:17:41 -0700, john larkin <jl@glen--canyon.com>
wrote:
I wonder why they did the SOAR graph with 6 volts on the gate.
Where does it say they did? The headline Rds value is given at a Tj
of 25 C. The SOA graph is with the junction(s) at max working temp.
There is nothing wrong with the graph.
The title of the SOAR graph clearly says Tc=25c.
But that's the external temperature, not the temperature of the
conducting channel inside the device,
Rds-on is typ 15 mohms, as shown in fig 6. The "limited by on-state
resistance" line is 40m all the way from 0.25 watts to 1 KW.
Because the conducting channel gets warmer when it is carrying more
current. Resistance isn't supposed to be current dependent, but when
there's enough current going through the conductor to warm it up, the
temperature dependence of the resistance does come into play.
The channel resistance is not going to be a nice stable 40 mOhm at all
currents, but the application engineer seems to have decided that 40
milliOhm was close enough
40 isn't very close to 15.
I'll just blow some up and see what they actually do.
Thinking about what's actually going on inside the devices as you blow
them up would let you get more information out of the exercise, but
might diminish the emotional gratification.
One good test is worth a thousand expert opinions.
- Wernher Von Braun
On Sun, 21 Jun 2026 08:03:16 -0700, john larkin <jl@glen--canyon.com>
wrote:
Take a look at the data sheet
https://www.digikey.com/en/products/detail/infineon-technologies/IPD180N10N3GATMA1/6599595
specifically fig 3, the SOAR curve.
The "limited by on-state resistance" line is about 40 mohms, but the
typical Rds-on value is 15.
The 10 millisecond line hits 1 amp and 30 volts, which is 30 watts.
But the part is rated for 71 watts.
I wonder what D = 0 means.
I guess I'll blow some up and see what they can really do.
John Larkin
Highland Tech Glen Canyon Design Center
Lunatic Fringe Electronics
Here's my little fet tester:
Actually, the fets should be fine. Spice says they will only dump 5 or
so mJ per shot at 50 amps each. I'm more concerned with damaging the
big 1 ohm thickfilm resistors, which are the laser diode current
limiters. Peak dissipation will be kilowatts per resistor.
Gate drive is from a 50 ohm DDG, so it's kinda slow. We'll use a
couple of beastly gate drivers on the real thing.
On 25/06/2026 5:11 am, john larkin wrote:
On Thu, 25 Jun 2026 02:12:01 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 25/06/2026 1:37 am, john larkin wrote:
On Wed, 24 Jun 2026 15:27:09 +0100, JM
<sunaecoNoChoppedPork@gmail.com> wrote:
On Wed, 24 Jun 2026 07:17:18 -0700, john larkin <jl@glen--canyon.com> >>>>> wrote:
On Tue, 23 Jun 2026 05:57:12 +0100, JM
<sunaecoNoChoppedPork@gmail.com> wrote:
On Mon, 22 Jun 2026 08:17:41 -0700, john larkin <jl@glen--canyon.com> >>>>>>> wrote:
I wonder why they did the SOAR graph with 6 volts on the gate. >>>>>>>>
Where does it say they did? The headline Rds value is given at a Tj >>>>>>> of 25 C. The SOA graph is with the junction(s) at max working temp. >>>>>>>
There is nothing wrong with the graph.
John Larkin
Highland Tech Glen Canyon Design Center
Lunatic Fringe Electronics
The title of the SOAR graph clearly says Tc=25c.
That is the case temperature. The whole point of the SOA graph is to >>>>> provide an indication of where parts of the die reach the maximum
operating temperature.
At a die teperature of 25 C.
Rds-on is typ 15 mohms, as shown in fig 6. The "limited by on-state >>>>>
What do you expect the die temp to be at 25c case temp and 0.25 watts
dissipation?
Read the data sheet.
resistance" line is 40m all the way from 0.25 watts to 1 KW.
I'll just blow some up and see what they actually do.
And how do you think Infineon measure the SOA?
Read the thermal instability paper by Berglio and Spirito.
When we tested a lot of big fets for our NMR drivers, we developed a
different thermal model. It worked fine.
Lots of different models work adequately.
<snipped uninformative advertising.>
Clamp mounted fets don't have a mounting screw hole, so there's more
room for silicon. Note: no insulators.
Why should we pay attention to the presence or absence of insulators?
Most FETs have lots of exposed metal so you can connect to gate, source
and drain. The gate connection doesn't have to carry a lot of current
except when the device is being turned on and off.
Insulators separate conductors that are carrying different currents, so
they are inevitable - your "Note: no insulators" is nonsense on the face >>> of it. You do need to learn to say what you mean, at least when you are
pretending to say something informative.
The thermal resistance of the insulators on that amp is exactly zero.
What you should have said was that the thermal resistance of the
electrical insulation between the FETs and the heat sinks on that amp is >exactly zero because ...
The fets are clamped onto copper bars, which spread the heat into the
aluminum heat sink.
Though it is "an" aluminium heat sink. There are bound to be others in
the immediate vicinity.
It's sort of irrelevant, because because the thermal interfaces between
the FETs and the eventual aluminium heatsinks are each contributing
their own small temperature rise along the thermal path.
Take a look at the data sheet
https://www.digikey.com/en/products/detail/infineon-technologies/IPD180N10N3GATMA1/6599595
specifically fig 3, the SOAR curve.
The "limited by on-state resistance" line is about 40 mohms, but the
typical Rds-on value is 15.
The 10 millisecond line hits 1 amp and 30 volts, which is 30 watts.
But the part is rated for 71 watts.
I wonder what D = 0 means.
I guess I'll blow some up and see what they can really do.
John Larkin
Highland Tech Glen Canyon Design Center
Lunatic Fringe Electronics
On Sun, 21 Jun 2026 08:03:16 -0700, john larkin <jl@glen--canyon.com>
wrote:
Take a look at the data sheet
https://www.digikey.com/en/products/detail/infineon-technologies/IPD180N10N3GATMA1/6599595
specifically fig 3, the SOAR curve.
The "limited by on-state resistance" line is about 40 mohms, but the
typical Rds-on value is 15.
The 10 millisecond line hits 1 amp and 30 volts, which is 30 watts.
But the part is rated for 71 watts.
I wonder what D = 0 means.
I guess I'll blow some up and see what they can really do.
John Larkin
Highland Tech Glen Canyon Design Center
Lunatic Fringe Electronics
Here's my test board.
https://www.dropbox.com/scl/fi/n551gftz44pry60gdg8u6/X134_thick_films.jpg?rlkey=r0dk16qms33sk8rgrgtsvz7fv&raw=1
There are two circuits, each a fet and a 1-ohm 35 watt Bourns
thickfilm resistor. I pulsed it at 60 volts, 2 usec, 250 Hz and both resistors failed after a couple of days. Fets are fine.
That's only 1.8 watts per resistor. Well, 3600 watts peak if you want
to get technical.
Thickfilms don't like big pulses.
On Thu, 25 Jun 2026 14:04:18 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 25/06/2026 5:11 am, john larkin wrote:
On Thu, 25 Jun 2026 02:12:01 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 25/06/2026 1:37 am, john larkin wrote:
On Wed, 24 Jun 2026 15:27:09 +0100, JM
<sunaecoNoChoppedPork@gmail.com> wrote:
On Wed, 24 Jun 2026 07:17:18 -0700, john larkin <jl@glen--canyon.com> >>>>>> wrote:
On Tue, 23 Jun 2026 05:57:12 +0100, JM
<sunaecoNoChoppedPork@gmail.com> wrote:
On Mon, 22 Jun 2026 08:17:41 -0700, john larkin <jl@glen--canyon.com> >>>>>>>> wrote:
I wonder why they did the SOAR graph with 6 volts on the gate. >>>>>>>>>
Where does it say they did? The headline Rds value is given at a Tj >>>>>>>> of 25 C. The SOA graph is with the junction(s) at max working temp. >>>>>>>>
There is nothing wrong with the graph.
John Larkin
Highland Tech Glen Canyon Design Center
Lunatic Fringe Electronics
The title of the SOAR graph clearly says Tc=25c.
That is the case temperature. The whole point of the SOA graph is to >>>>>> provide an indication of where parts of the die reach the maximum
operating temperature.
At a die teperature of 25 C.
Rds-on is typ 15 mohms, as shown in fig 6. The "limited by on-state >>>>>>
What do you expect the die temp to be at 25c case temp and 0.25 watts >>>>> dissipation?
Read the data sheet.
resistance" line is 40m all the way from 0.25 watts to 1 KW.
I'll just blow some up and see what they actually do.
And how do you think Infineon measure the SOA?
Read the thermal instability paper by Berglio and Spirito.
When we tested a lot of big fets for our NMR drivers, we developed a >>>>> different thermal model. It worked fine.
Lots of different models work adequately.
<snipped uninformative advertising.>
Clamp mounted fets don't have a mounting screw hole, so there's more >>>>> room for silicon. Note: no insulators.
Why should we pay attention to the presence or absence of insulators?
Most FETs have lots of exposed metal so you can connect to gate, source >>>> and drain. The gate connection doesn't have to carry a lot of current
except when the device is being turned on and off.
Insulators separate conductors that are carrying different currents, so >>>> they are inevitable - your "Note: no insulators" is nonsense on the face >>>> of it. You do need to learn to say what you mean, at least when you are >>>> pretending to say something informative.
The thermal resistance of the insulators on that amp is exactly zero.
What you should have said was that the thermal resistance of the
electrical insulation between the FETs and the heat sinks on that amp is
exactly zero because ...
Because there are no insulators. The 16 p-channel fets and 16
n-channel fets are hard-clamped to the heat sink, which is the amp
output node.
The fets are clamped onto copper bars, which spread the heat into the
aluminum heat sink.
Though it is "an" aluminium heat sink. There are bound to be others in
the immediate vicinity.
Not in my box.
It's sort of irrelevant, because because the thermal interfaces between
the FETs and the eventual aluminium heatsinks are each contributing
their own small temperature rise along the thermal path.
The copper heat spreaders were machined very flat. Aluminum extrusions
are typically not especially flat, so one can get serious air gaps
against a big fet. The fets are very flat themselves.
Hold a big fet against a commercial aluminum heat sink and peek at it edgewise. You can usually see light through the gap.
On 27/06/2026 4:50 am, john larkin wrote:
On Thu, 25 Jun 2026 14:04:18 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 25/06/2026 5:11 am, john larkin wrote:
On Thu, 25 Jun 2026 02:12:01 +1000, Bill Sloman <bill.sloman@ieee.org> >>>> wrote:
On 25/06/2026 1:37 am, john larkin wrote:
On Wed, 24 Jun 2026 15:27:09 +0100, JM
<sunaecoNoChoppedPork@gmail.com> wrote:
On Wed, 24 Jun 2026 07:17:18 -0700, john larkin <jl@glen--canyon.com> >>>>>>> wrote:
On Tue, 23 Jun 2026 05:57:12 +0100, JM
<sunaecoNoChoppedPork@gmail.com> wrote:
On Mon, 22 Jun 2026 08:17:41 -0700, john larkin <jl@glen--canyon.com> >>>>>>>>> wrote:
I wonder why they did the SOAR graph with 6 volts on the gate. >>>>>>>>>>
Where does it say they did? The headline Rds value is given at a Tj >>>>>>>>> of 25 C. The SOA graph is with the junction(s) at max working temp. >>>>>>>>>
There is nothing wrong with the graph.
John Larkin
Highland Tech Glen Canyon Design Center
Lunatic Fringe Electronics
The title of the SOAR graph clearly says Tc=25c.
That is the case temperature. The whole point of the SOA graph is to >>>>>>> provide an indication of where parts of the die reach the maximum >>>>>>> operating temperature.
At a die teperature of 25 C.
Rds-on is typ 15 mohms, as shown in fig 6. The "limited by on-state >>>>>>>
What do you expect the die temp to be at 25c case temp and 0.25 watts >>>>>> dissipation?
Read the data sheet.
resistance" line is 40m all the way from 0.25 watts to 1 KW.
I'll just blow some up and see what they actually do.
And how do you think Infineon measure the SOA?
Read the thermal instability paper by Berglio and Spirito.
When we tested a lot of big fets for our NMR drivers, we developed a >>>>>> different thermal model. It worked fine.
Lots of different models work adequately.
<snipped uninformative advertising.>
Clamp mounted fets don't have a mounting screw hole, so there's more >>>>>> room for silicon. Note: no insulators.
Why should we pay attention to the presence or absence of insulators? >>>>>
Most FETs have lots of exposed metal so you can connect to gate, source >>>>> and drain. The gate connection doesn't have to carry a lot of current >>>>> except when the device is being turned on and off.
Insulators separate conductors that are carrying different currents, so >>>>> they are inevitable - your "Note: no insulators" is nonsense on the face >>>>> of it. You do need to learn to say what you mean, at least when you are >>>>> pretending to say something informative.
The thermal resistance of the insulators on that amp is exactly zero.
What you should have said was that the thermal resistance of the
electrical insulation between the FETs and the heat sinks on that amp is >>> exactly zero because ...
Because there are no insulators. The 16 p-channel fets and 16
n-channel fets are hard-clamped to the heat sink, which is the amp
output node.
The fets are clamped onto copper bars, which spread the heat into the
aluminum heat sink.
Though it is "an" aluminium heat sink. There are bound to be others in
the immediate vicinity.
Not in my box.
Minimalist.
It's sort of irrelevant, because because the thermal interfaces between
the FETs and the eventual aluminium heatsinks are each contributing
their own small temperature rise along the thermal path.
The copper heat spreaders were machined very flat. Aluminum extrusions
are typically not especially flat, so one can get serious air gaps
against a big fet. The fets are very flat themselves.
Hold a big fet against a commercial aluminum heat sink and peek at it
edgewise. You can usually see light through the gap.
That's why people put zinc-oxide loaded silicone grease between
components and heat sinks. It's not as conductive as metal, but it's a
lot more conductive than air. It is also called "thermal contact
compound" and 'heat sink grease" for the benefit of people like you.
On 27/06/2026 6:24 am, john larkin wrote:
On Sun, 21 Jun 2026 08:03:16 -0700, john larkin <jl@glen--canyon.com>
wrote:
Take a look at the data sheet
https://www.digikey.com/en/products/detail/infineon-technologies/IPD180N10N3GATMA1/6599595
specifically fig 3, the SOAR curve.
The "limited by on-state resistance" line is about 40 mohms, but the
typical Rds-on value is 15.
The 10 millisecond line hits 1 amp and 30 volts, which is 30 watts.
But the part is rated for 71 watts.
I wonder what D = 0 means.
I guess I'll blow some up and see what they can really do.
John Larkin
Highland Tech Glen Canyon Design Center
Lunatic Fringe Electronics
Here's my test board.
https://www.dropbox.com/scl/fi/n551gftz44pry60gdg8u6/X134_thick_films.jpg?rlkey=r0dk16qms33sk8rgrgtsvz7fv&raw=1
There are two circuits, each a fet and a 1-ohm 35 watt Bourns
thickfilm resistor. I pulsed it at 60 volts, 2 usec, 250 Hz and both
resistors failed after a couple of days. Fets are fine.
That's only 1.8 watts per resistor. Well, 3600 watts peak if you want
to get technical.
Thickfilms don't like big pulses.
Nothing likes big pulses. With short pulses all the power dissipated in
the resistor stays in the resistive element (a least for a few
microseconds) and the question is how hot can you let the resistive
element get before it expands enough to exceed the local elastic limit.
Thick films have a more massive resistive element than thin film
resistors, but it is still a film. The aim is to have enough resistor
area that none of it gets hot enough to get stressed to the point of >irreversible mechanical movement. Putting in four equal value resistors
as two parallel pairs in series would get you started. You could stack
them on top of one another (if your rep rate was low enough). The sky is
the limit.
We're thinking that nichrome wire would be pretty tough, namely a
wirewould resistor. I'm testing some now and they seem fine.
Next we'll need a tiny fan.
The microstructure of thickfilms seems to make them vulnerable to
progressive damage from short high-power pulses. They seem to grow
surface cracks over time, especially near laser trims that cause
current crowding. I saw that during my RF attenuator experiments too,
9KW pulses.
On Mon, 29 Jun 2026 15:56:33 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 27/06/2026 4:50 am, john larkin wrote:
On Thu, 25 Jun 2026 14:04:18 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 25/06/2026 5:11 am, john larkin wrote:
On Thu, 25 Jun 2026 02:12:01 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>> wrote:What you should have said was that the thermal resistance of the
On 25/06/2026 1:37 am, john larkin wrote:
On Wed, 24 Jun 2026 15:27:09 +0100, JM
<sunaecoNoChoppedPork@gmail.com> wrote:
On Wed, 24 Jun 2026 07:17:18 -0700, john larkin <jl@glen--canyon.com> >>>>>>>> wrote:
On Tue, 23 Jun 2026 05:57:12 +0100, JM
<sunaecoNoChoppedPork@gmail.com> wrote:
On Mon, 22 Jun 2026 08:17:41 -0700, john larkin <jl@glen--canyon.com>
wrote:
I wonder why they did the SOAR graph with 6 volts on the gate. >>>>>>>>>>>
Where does it say they did? The headline Rds value is given at a Tj >>>>>>>>>> of 25 C. The SOA graph is with the junction(s) at max working temp. >>>>>>>>>>
There is nothing wrong with the graph.
John Larkin
Highland Tech Glen Canyon Design Center
Lunatic Fringe Electronics
The title of the SOAR graph clearly says Tc=25c.
That is the case temperature. The whole point of the SOA graph is to >>>>>>>> provide an indication of where parts of the die reach the maximum >>>>>>>> operating temperature.
At a die teperature of 25 C.
Rds-on is typ 15 mohms, as shown in fig 6. The "limited by on-state >>>>>>>>
What do you expect the die temp to be at 25c case temp and 0.25 watts >>>>>>> dissipation?
Read the data sheet.
resistance" line is 40m all the way from 0.25 watts to 1 KW. >>>>>>>>>
I'll just blow some up and see what they actually do.
And how do you think Infineon measure the SOA?
Read the thermal instability paper by Berglio and Spirito.
When we tested a lot of big fets for our NMR drivers, we developed a >>>>>>> different thermal model. It worked fine.
Lots of different models work adequately.
<snipped uninformative advertising.>
Clamp mounted fets don't have a mounting screw hole, so there's more >>>>>>> room for silicon. Note: no insulators.
Why should we pay attention to the presence or absence of insulators? >>>>>>
Most FETs have lots of exposed metal so you can connect to gate, source >>>>>> and drain. The gate connection doesn't have to carry a lot of current >>>>>> except when the device is being turned on and off.
Insulators separate conductors that are carrying different currents, so >>>>>> they are inevitable - your "Note: no insulators" is nonsense on the face >>>>>> of it. You do need to learn to say what you mean, at least when you are >>>>>> pretending to say something informative.
The thermal resistance of the insulators on that amp is exactly zero. >>>>
electrical insulation between the FETs and the heat sinks on that amp is >>>> exactly zero because ...
Because there are no insulators. The 16 p-channel fets and 16
n-channel fets are hard-clamped to the heat sink, which is the amp
output node.
The fets are clamped onto copper bars, which spread the heat into the >>>>> aluminum heat sink.
Though it is "an" aluminium heat sink. There are bound to be others in >>>> the immediate vicinity.
Not in my box.
Minimalist.
It's sort of irrelevant, because because the thermal interfaces between >>>> the FETs and the eventual aluminium heatsinks are each contributing
their own small temperature rise along the thermal path.
The copper heat spreaders were machined very flat. Aluminum extrusions
are typically not especially flat, so one can get serious air gaps
against a big fet. The fets are very flat themselves.
Hold a big fet against a commercial aluminum heat sink and peek at it
edgewise. You can usually see light through the gap.
That's why people put zinc-oxide loaded silicone grease between
components and heat sinks. It's not as conductive as metal, but it's a
lot more conductive than air. It is also called "thermal contact
compound" and 'heat sink grease" for the benefit of people like you.
A couple of mils gap of filled silicone grease will seriously increase
theta and junction temperature. We know because we measured it. The
best grease is still a rotten heat conductor.
We even tried diamond-filled grease. It's not much better than the
regular stuff. Do you know why?
The fets are shipped very flat; extrusions aren't. If the heat sink,
or in our case the copper spreaders, are machined flat, the gap and
grease can squish down below 100 micro-inches.
Once you fix the gap problem, the big problem becomes the spreading
thermal resistance of the aluminum itself. Extrudable aluminum alloys
don't conduct heat nearly as well as textbook "aluminum" numbers.
Hence the machined flat copper heat speaders. There are some
machinable copper alloys that conduct heat almost as well as pure
copper.
All the above was confirmed by experiment. We sold a lot of gradient
drivers and they were reliable.
On Mon, 29 Jun 2026 12:55:23 -0700, john larkin <jl@glen--canyon.com>
wrote:
We're thinking that nichrome wire would be pretty tough, namely a
wirewould resistor. I'm testing some now and they seem fine.
Next we'll need a tiny fan.
The microstructure of thickfilms seems to make them vulnerable to
progressive damage from short high-power pulses. They seem to grow
surface cracks over time, especially near laser trims that cause
current crowding. I saw that during my RF attenuator experiments too,
9KW pulses.
For 2us pulses?
What is your long term accuracy requirements?
I would have thought carbon MELFs would have been fine. And cheaper.
Once you fix the gap problem, the big problem becomes the spreading
thermal resistance of the aluminum itself. Extrudable aluminum alloys
don't conduct heat nearly as well as textbook "aluminum" numbers.
Hence the machined flat copper heat speaders.
john larkin <jl@glen--canyon.com> wrote:
[...]
Once you fix the gap problem, the big problem becomes the spreading
thermal resistance of the aluminum itself. Extrudable aluminum alloys
don't conduct heat nearly as well as textbook "aluminum" numbers.
Hence the machined flat copper heat speaders.
Would it be better to anneal the copper after machining, so as to
relieve the stresses and make it more malleable? It would then flow
and conform to the surface of the devices even better than just a
machined surface.
On 30/06/2026 11:38 am, JM wrote:
On Mon, 29 Jun 2026 12:55:23 -0700, john larkin <jl@glen--canyon.com>
wrote:
We're thinking that nichrome wire would be pretty tough, namely a
wirewould resistor. I'm testing some now and they seem fine.
But inductive. There are non-inductive winding schemes, but they tend to
be more less-inductive than non-inductive.
Next we'll need a tiny fan.
The microstructure of thickfilms seems to make them vulnerable to
progressive damage from short high-power pulses. They seem to grow
surface cracks over time, especially near laser trims that cause
current crowding. I saw that during my RF attenuator experiments too,
9KW pulses.
For 2us pulses?
What is your long term accuracy requirements?
I would have thought carbon MELFs would have been fine. And cheaper.
Carbon resistors have a negative temperature coefficient of resistance,
and if you drive them sufficiently hard, you concentrate the current
into hot channels.
You can't use them in intrinsically safe designs for that reason. Early
on one Colin Hunter, who had sat on the intrinsic safety committee,
showed us a demonstration set-up up that put 1A through a 10k 600mW film >resistor for a few minutes. It still measure 10k afterwards, but there
was a narrow dark line on the colour bands where the hot channel had formed.
You can form the hot channels very quickly - Colin Hunter's
demonstration depended on that. The core of a hot channel is a very
narrow path indeed and doesn't have much thermal mass.
There's a upper limit on the current you can put through an NTC
thermistor for exactly the same reason, though the problem doesn't show
up as a hot channel but rather as an instability of resistance as the >various possible current paths change resistance as the different
regions within the thermistor warm up differently.
On 30/06/2026 09:04, Liz Tuddenham wrote:
john larkin <jl@glen--canyon.com> wrote:
[...]
Once you fix the gap problem, the big problem becomes the spreading
thermal resistance of the aluminum itself. Extrudable aluminum alloys
don't conduct heat nearly as well as textbook "aluminum" numbers.
Hence the machined flat copper heat speaders.
Would it be better to anneal the copper after machining, so as to
relieve the stresses and make it more malleable?-a It would then-a flow
and conform to the surface of the devices even better than just a
machined surface.
For the ultimate thermal contact, machine the surface flat and then
interpose a thin layer of pure gold between the copper heat
spreader and the copper base of the transistor.-a Heating this under
pressure will create a diffusion weld. The pressure could come from
the mounting clips.-a The gold could be electroplated so as to avoid
having to handle delicate gold leaf.-a Avoid using the type of gold
used for pcb edge contacts as this contains a small amount of
nickel or cobalt to harden it.-a It might be necessary to strip off
the tin plating from the transistor heat sink tab for this to work
properly.
Back in the real world, simply soldering the transistors onto the
copper heat spreader might be almost as effective.
On Tue, 30 Jun 2026 16:53:49 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 30/06/2026 11:38 am, JM wrote:
On Mon, 29 Jun 2026 12:55:23 -0700, john larkin <jl@glen--canyon.com>
wrote:
We're thinking that nichrome wire would be pretty tough, namely a
wirewould resistor. I'm testing some now and they seem fine.
But inductive. There are non-inductive winding schemes, but they tend to >>be more less-inductive than non-inductive.
The 1-ohm 5-watt surface mount part that I'm testing measures 220 nH,
and I'll use two, essentially in parallel. That's OK for my laser
driver.
In another product I put two inductors nearby, which doubles the net >inductance. If I flip the direction of one, it will reduce inductance.
Next we'll need a tiny fan.
The microstructure of thickfilms seems to make them vulnerable to
progressive damage from short high-power pulses. They seem to grow
surface cracks over time, especially near laser trims that cause
current crowding. I saw that during my RF attenuator experiments too,
9KW pulses.
For 2us pulses?
What is your long term accuracy requirements?
I would have thought carbon MELFs would have been fine. And cheaper.
Carbon resistors have a negative temperature coefficient of resistance, >>and if you drive them sufficiently hard, you concentrate the current
into hot channels.
You can't use them in intrinsically safe designs for that reason. Early
on one Colin Hunter, who had sat on the intrinsic safety committee,
showed us a demonstration set-up up that put 1A through a 10k 600mW film >>resistor for a few minutes. It still measure 10k afterwards, but there
was a narrow dark line on the colour bands where the hot channel had formed. >>
You can form the hot channels very quickly - Colin Hunter's
demonstration depended on that. The core of a hot channel is a very
narrow path indeed and doesn't have much thermal mass.
There's a upper limit on the current you can put through an NTC
thermistor for exactly the same reason, though the problem doesn't show
up as a hot channel but rather as an instability of resistance as the >>various possible current paths change resistance as the different
regions within the thermistor warm up differently.
Right. I expect that any material with an amorphous film element will
be damaged by big power pulses.
John Larkin
Highland Tech Glen Canyon Design Center
Lunatic Fringe Electronics
On 30/06/2026 7:51 pm, John R Walliker wrote:
On 30/06/2026 09:04, Liz Tuddenham wrote:
john larkin <jl@glen--canyon.com> wrote:
[...]
Once you fix the gap problem, the big problem becomes the spreading
thermal resistance of the aluminum itself. Extrudable aluminum alloys
don't conduct heat nearly as well as textbook "aluminum" numbers.
Hence the machined flat copper heat speaders.
Would it be better to anneal the copper after machining, so as to
relieve the stresses and make it more malleable?-a It would then-a flow
and conform to the surface of the devices even better than just a
machined surface.
For the ultimate thermal contact, machine the surface flat and then
interpose a thin layer of pure gold between the copper heat
spreader and the copper base of the transistor.-a Heating this under
pressure will create a diffusion weld. The pressure could come from
the mounting clips.-a The gold could be electroplated so as to avoid
having to handle delicate gold leaf.-a Avoid using the type of gold
used for pcb edge contacts as this contains a small amount of
nickel or cobalt to harden it.-a It might be necessary to strip off
the tin plating from the transistor heat sink tab for this to work
properly.
Back in the real world, simply soldering the transistors onto the
copper heat spreader might be almost as effective.
It might also effectively wreck the transistors.
Transistors are made by forming semiconducting junction by doping the silicon surface. Make the device hot enough for long enough and the
dopants move around.
Soldering surface mount components onto a printed circuit requires you
to set up a thermal profile that guarantees that the active components aren't too hot for too long.
On 30/06/2026 12:56 am, john larkin wrote:
On Mon, 29 Jun 2026 15:56:33 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 27/06/2026 4:50 am, john larkin wrote:
On Thu, 25 Jun 2026 14:04:18 +1000, Bill Sloman <bill.sloman@ieee.org> >>>> wrote:
On 25/06/2026 5:11 am, john larkin wrote:
On Thu, 25 Jun 2026 02:12:01 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>> wrote:What you should have said was that the thermal resistance of the
On 25/06/2026 1:37 am, john larkin wrote:
On Wed, 24 Jun 2026 15:27:09 +0100, JM
<sunaecoNoChoppedPork@gmail.com> wrote:
On Wed, 24 Jun 2026 07:17:18 -0700, john larkin <jl@glen--canyon.com> >>>>>>>>> wrote:
On Tue, 23 Jun 2026 05:57:12 +0100, JM
<sunaecoNoChoppedPork@gmail.com> wrote:
On Mon, 22 Jun 2026 08:17:41 -0700, john larkin <jl@glen--canyon.com>
wrote:
I wonder why they did the SOAR graph with 6 volts on the gate. >>>>>>>>>>>>
Where does it say they did? The headline Rds value is given at a Tj
of 25 C. The SOA graph is with the junction(s) at max working temp.
There is nothing wrong with the graph.
John Larkin
Highland Tech Glen Canyon Design Center
Lunatic Fringe Electronics
The title of the SOAR graph clearly says Tc=25c.
That is the case temperature. The whole point of the SOA graph is to >>>>>>>>> provide an indication of where parts of the die reach the maximum >>>>>>>>> operating temperature.
At a die teperature of 25 C.
Rds-on is typ 15 mohms, as shown in fig 6. The "limited by on-state >>>>>>>>>
What do you expect the die temp to be at 25c case temp and 0.25 watts >>>>>>>> dissipation?
Read the data sheet.
resistance" line is 40m all the way from 0.25 watts to 1 KW. >>>>>>>>>>
I'll just blow some up and see what they actually do.
And how do you think Infineon measure the SOA?
Read the thermal instability paper by Berglio and Spirito.
When we tested a lot of big fets for our NMR drivers, we developed a >>>>>>>> different thermal model. It worked fine.
Lots of different models work adequately.
<snipped uninformative advertising.>
Clamp mounted fets don't have a mounting screw hole, so there's more >>>>>>>> room for silicon. Note: no insulators.
Why should we pay attention to the presence or absence of insulators? >>>>>>>
Most FETs have lots of exposed metal so you can connect to gate, source >>>>>>> and drain. The gate connection doesn't have to carry a lot of current >>>>>>> except when the device is being turned on and off.
Insulators separate conductors that are carrying different currents, so >>>>>>> they are inevitable - your "Note: no insulators" is nonsense on the face
of it. You do need to learn to say what you mean, at least when you are >>>>>>> pretending to say something informative.
The thermal resistance of the insulators on that amp is exactly zero. >>>>>
electrical insulation between the FETs and the heat sinks on that amp is >>>>> exactly zero because ...
Because there are no insulators. The 16 p-channel fets and 16
n-channel fets are hard-clamped to the heat sink, which is the amp
output node.
The fets are clamped onto copper bars, which spread the heat into the >>>>>> aluminum heat sink.
Though it is "an" aluminium heat sink. There are bound to be others in >>>>> the immediate vicinity.
Not in my box.
Minimalist.
It's sort of irrelevant, because because the thermal interfaces between >>>>> the FETs and the eventual aluminium heatsinks are each contributing
their own small temperature rise along the thermal path.
The copper heat spreaders were machined very flat. Aluminum extrusions >>>> are typically not especially flat, so one can get serious air gaps
against a big fet. The fets are very flat themselves.
Hold a big fet against a commercial aluminum heat sink and peek at it
edgewise. You can usually see light through the gap.
That's why people put zinc-oxide loaded silicone grease between
components and heat sinks. It's not as conductive as metal, but it's a
lot more conductive than air. It is also called "thermal contact
compound" and 'heat sink grease" for the benefit of people like you.
A couple of mils gap of filled silicone grease will seriously increase
theta and junction temperature. We know because we measured it. The
best grease is still a rotten heat conductor.
But still a whole lot better than air.>
We even tried diamond-filled grease. It's not much better than the
regular stuff. Do you know why?
You'd need very regular bits of diamonds to make a difference
https://en.wikipedia.org/wiki/Space-filling_polyhedron
and they wouldn't pack tightly enough to do much good without help.
The fets are shipped very flat; extrusions aren't. If the heat sink,
or in our case the copper spreaders, are machined flat, the gap and
grease can squish down below 100 micro-inches.
Once you fix the gap problem, the big problem becomes the spreading
thermal resistance of the aluminum itself. Extrudable aluminum alloys
don't conduct heat nearly as well as textbook "aluminum" numbers.
Hence the machined flat copper heat speaders. There are some
machinable copper alloys that conduct heat almost as well as pure
copper.
All the above was confirmed by experiment. We sold a lot of gradient
drivers and they were reliable.
The two statements aren't necessarily related. Badly constructed
experiments can mislead potential customers. You obviously produced
adequate gradient drivers. This makes them adequately designed.
Optimisation requires a fairly deep understanding of what you are doing,
and it's rarely worth expending that much effort for a relatively small >market. The last time I was in hospital - for just two days - I was
scanned a couple of times, so the market may be growing. If you aren't
still selling gradient drivers, maybe someone else put in the extra effort.
john larkin <jl@glen--canyon.com>wrote:
On Tue, 30 Jun 2026 07:22:13 -0700, john larkin <jl@glen--canyon.com>wrote:
This is cool,
https://www.digikey.com/en/products/detail/ohmite/WHE1R0FET/16838861
1 ohm 1% 5 watts < 1 nH 32 cents
On Tue, 30 Jun 2026 16:53:49 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 30/06/2026 11:38 am, JM wrote:
On Mon, 29 Jun 2026 12:55:23 -0700, john larkin <jl@glen--canyon.com>
wrote:
I would have thought carbon MELFs would have been fine. And cheaper.
Carbon resistors have a negative temperature coefficient of resistance,
and if you drive them sufficiently hard, you concentrate the current
into hot channels.
You can't use them in intrinsically safe designs for that reason. Early
on one Colin Hunter, who had sat on the intrinsic safety committee,
showed us a demonstration set-up up that put 1A through a 10k 600mW film
resistor for a few minutes. It still measure 10k afterwards, but there
was a narrow dark line on the colour bands where the hot channel had formed. >>
You can form the hot channels very quickly - Colin Hunter's
demonstration depended on that. The core of a hot channel is a very
narrow path indeed and doesn't have much thermal mass.
There's a upper limit on the current you can put through an NTC
thermistor for exactly the same reason, though the problem doesn't show
up as a hot channel but rather as an instability of resistance as the
various possible current paths change resistance as the different
regions within the thermistor warm up differently.
Right. I expect that any material with an amorphous film element will
be damaged by big power pulses.
john larkin <jl@glen--canyon.com>wrote:
On Tue, 30 Jun 2026 07:22:13 -0700, john larkin <jl@glen--canyon.com> >>wrote:This is cool,
https://www.digikey.com/en/products/detail/ohmite/WHE1R0FET/16838861
1 ohm 1% 5 watts < 1 nH 32 cents
It is wirewound,
combined with local capacitance it may well resonate in the GHz range.
On 1/07/2026 12:22 am, john larkin wrote:
On Tue, 30 Jun 2026 16:53:49 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 30/06/2026 11:38 am, JM wrote:
On Mon, 29 Jun 2026 12:55:23 -0700, john larkin <jl@glen--canyon.com>
wrote:
<snip>
I would have thought carbon MELFs would have been fine. And cheaper.
Carbon resistors have a negative temperature coefficient of resistance,
and if you drive them sufficiently hard, you concentrate the current
into hot channels.
You can't use them in intrinsically safe designs for that reason. Early
on one Colin Hunter, who had sat on the intrinsic safety committee,
showed us a demonstration set-up up that put 1A through a 10k 600mW film >>> resistor for a few minutes. It still measure 10k afterwards, but there
was a narrow dark line on the colour bands where the hot channel had formed.
You can form the hot channels very quickly - Colin Hunter's
demonstration depended on that. The core of a hot channel is a very
narrow path indeed and doesn't have much thermal mass.
There's a upper limit on the current you can put through an NTC
thermistor for exactly the same reason, though the problem doesn't show
up as a hot channel but rather as an instability of resistance as the
various possible current paths change resistance as the different
regions within the thermistor warm up differently.
Right. I expect that any material with an amorphous film element will
be damaged by big power pulses.
You missed the point. If the amorphous film element has negative
temperature coefficient of resistance, it won't be damaged - it will
just form a hot channel and let lots of current through without
sustaining any permanent damage, though anything in series with it may
not be as lucky. Once the hot channel cools down it will work just as it
did before.
On Wed, 1 Jul 2026 17:05:38 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 1/07/2026 12:22 am, john larkin wrote:
On Tue, 30 Jun 2026 16:53:49 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 30/06/2026 11:38 am, JM wrote:
On Mon, 29 Jun 2026 12:55:23 -0700, john larkin <jl@glen--canyon.com> >>>>> wrote:
<snip>
I would have thought carbon MELFs would have been fine. And cheaper. >>>>Carbon resistors have a negative temperature coefficient of resistance, >>>> and if you drive them sufficiently hard, you concentrate the current
into hot channels.
You can't use them in intrinsically safe designs for that reason. Early >>>> on one Colin Hunter, who had sat on the intrinsic safety committee,
showed us a demonstration set-up up that put 1A through a 10k 600mW film >>>> resistor for a few minutes. It still measure 10k afterwards, but there >>>> was a narrow dark line on the colour bands where the hot channel had formed.
You can form the hot channels very quickly - Colin Hunter's
demonstration depended on that. The core of a hot channel is a very
narrow path indeed and doesn't have much thermal mass.
There's a upper limit on the current you can put through an NTC
thermistor for exactly the same reason, though the problem doesn't show >>>> up as a hot channel but rather as an instability of resistance as the
various possible current paths change resistance as the different
regions within the thermistor warm up differently.
Right. I expect that any material with an amorphous film element will
be damaged by big power pulses.
You missed the point. If the amorphous film element has negative
temperature coefficient of resistance, it won't be damaged - it will
just form a hot channel and let lots of current through without
sustaining any permanent damage, though anything in series with it may
not be as lucky. Once the hot channel cools down it will work just as it
did before.
Multiple experiments consistently disagree.
Try it.
That's why people put zinc-oxide loaded silicone grease between
components and heat sinks. It's not as conductive as metal, but it's a
lot more conductive than air. It is also called "thermal contact
compound" and 'heat sink grease" for the benefit of people like you.
A couple of mils gap of filled silicone gease will seriously increase
theta and junction temperature. We know because we measured it. The
best grease is still a rotten heat conductor.
We even tried diamond-filled grease. It's not much better than the
regular stuff. Do you know why?
The fets are shipped very flat; extrusions aren't. If the heat sink,
or in our case the copper spreaders, are machined flat, the gap and
gease can squish down below 100 micro-inches.
Once you fix the gap problem, the big problem becomes the spreading
thermal resistance of the aluminum itself. Extrudable aluminum alloys
don't conduct heat nearly as well as textbook "aluminum" numbers.
Hence the machined flat copper heat speaders. There are some
machinable copper alloys that conduct heat almost as well as pure
copper.
All the above was confirmed by experiment. We sold a lot of gradient
drivers and they were reliable.
John Larkin
Highland Tech Glen Canyon Design Center
Lunatic Fringe Electronics
... Lots of
complex stuff full of avalanche transistors, varicaps, SRDs, DSRDs,
SiC fets, transmission lines. Yes, fun stuff.
https://www.dropbox.com/scl/fi/2uqqmt4ag4up7jsl7u7yu/s-l1600-1.jpg?rlkey=udsbfvyp2bzzpgfkyvtv58eyy&raw=1
But not very manufacturable.
On 6/23/2026 8:20 AM, john larkin wrote:
... Lots of
complex stuff full of avalanche transistors, varicaps, SRDs, DSRDs,
SiC fets, transmission lines. Yes, fun stuff.
https://www.dropbox.com/scl/fi/2uqqmt4ag4up7jsl7u7yu/s-l1600-1.jpg?rlkey=udsbfvyp2bzzpgfkyvtv58eyy&raw=1
But not very manufacturable.
Curious to know if these boxes are rated by a safety agency? (TUV, CSA, UL, etc.)
I see the CSA logo on the AC power entry module, but don't know if the whole box
itself needs approval. One company I worked for had a safety engineering >group that I could never pin down to give me an answer what the rules were.
On Mon, 29 Jun 2026 07:56:28 -0700, john larkin <jl@glen--canyon.com>
wrote:
<snip>
That's why people put zinc-oxide loaded silicone grease between >>>components and heat sinks. It's not as conductive as metal, but it's a >>>lot more conductive than air. It is also called "thermal contact >>>compound" and 'heat sink grease" for the benefit of people like you.
A couple of mils gap of filled silicone gease will seriously increase
theta and junction temperature. We know because we measured it. The
best grease is still a rotten heat conductor.
We even tried diamond-filled grease. It's not much better than the
regular stuff. Do you know why?
The fets are shipped very flat; extrusions aren't. If the heat sink,
or in our case the copper spreaders, are machined flat, the gap and
gease can squish down below 100 micro-inches.
Once you fix the gap problem, the big problem becomes the spreading
thermal resistance of the aluminum itself. Extrudable aluminum alloys
don't conduct heat nearly as well as textbook "aluminum" numbers.
Hence the machined flat copper heat speaders. There are some
machinable copper alloys that conduct heat almost as well as pure
copper.
All the above was confirmed by experiment. We sold a lot of gradient >>drivers and they were reliable.
John Larkin
Highland Tech Glen Canyon Design Center
Lunatic Fringe Electronics
Sounds like you're not insulating the heat source.
If so, then a soft copper foil introduced between the
device and an aluminum spreader works pretty well as
a gap filler and a conductive interface.
RL
On 1/07/2026 8:50 pm, john larkin wrote:
On Wed, 1 Jul 2026 17:05:38 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 1/07/2026 12:22 am, john larkin wrote:
On Tue, 30 Jun 2026 16:53:49 +1000, Bill Sloman <bill.sloman@ieee.org> >>>> wrote:
On 30/06/2026 11:38 am, JM wrote:
On Mon, 29 Jun 2026 12:55:23 -0700, john larkin <jl@glen--canyon.com> >>>>>> wrote:
<snip>
I would have thought carbon MELFs would have been fine. And cheaper. >>>>>Carbon resistors have a negative temperature coefficient of resistance, >>>>> and if you drive them sufficiently hard, you concentrate the current >>>>> into hot channels.
You can't use them in intrinsically safe designs for that reason. Early >>>>> on one Colin Hunter, who had sat on the intrinsic safety committee,
showed us a demonstration set-up up that put 1A through a 10k 600mW film >>>>> resistor for a few minutes. It still measure 10k afterwards, but there >>>>> was a narrow dark line on the colour bands where the hot channel had formed.
You can form the hot channels very quickly - Colin Hunter's
demonstration depended on that. The core of a hot channel is a very
narrow path indeed and doesn't have much thermal mass.
There's a upper limit on the current you can put through an NTC
thermistor for exactly the same reason, though the problem doesn't show >>>>> up as a hot channel but rather as an instability of resistance as the >>>>> various possible current paths change resistance as the different
regions within the thermistor warm up differently.
Right. I expect that any material with an amorphous film element will
be damaged by big power pulses.
You missed the point. If the amorphous film element has negative
temperature coefficient of resistance, it won't be damaged - it will
just form a hot channel and let lots of current through without
sustaining any permanent damage, though anything in series with it may
not be as lucky. Once the hot channel cools down it will work just as it >>> did before.
Multiple experiments consistently disagree.
Try it.
The experiment in about 1975 that I witnessed did not destroy the carbon >film resistor. It was carefully designed to show how hot channels
worked. A less expert experimenter might not have got the same result,
and a less receptive audience might not have understood what was being >demonstrated.
On Wed, 1 Jul 2026 21:41:30 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 1/07/2026 8:50 pm, john larkin wrote:
On Wed, 1 Jul 2026 17:05:38 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 1/07/2026 12:22 am, john larkin wrote:
On Tue, 30 Jun 2026 16:53:49 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>> wrote:
On 30/06/2026 11:38 am, JM wrote:
On Mon, 29 Jun 2026 12:55:23 -0700, john larkin <jl@glen--canyon.com> >>>>>>> wrote:
<snip>
I would have thought carbon MELFs would have been fine. And cheaper. >>>>>>Carbon resistors have a negative temperature coefficient of resistance, >>>>>> and if you drive them sufficiently hard, you concentrate the current >>>>>> into hot channels.
You can't use them in intrinsically safe designs for that reason. Early >>>>>> on one Colin Hunter, who had sat on the intrinsic safety committee, >>>>>> showed us a demonstration set-up up that put 1A through a 10k 600mW film >>>>>> resistor for a few minutes. It still measure 10k afterwards, but there >>>>>> was a narrow dark line on the colour bands where the hot channel had formed.
You can form the hot channels very quickly - Colin Hunter's
demonstration depended on that. The core of a hot channel is a very >>>>>> narrow path indeed and doesn't have much thermal mass.
There's a upper limit on the current you can put through an NTC
thermistor for exactly the same reason, though the problem doesn't show >>>>>> up as a hot channel but rather as an instability of resistance as the >>>>>> various possible current paths change resistance as the different
regions within the thermistor warm up differently.
Right. I expect that any material with an amorphous film element will >>>>> be damaged by big power pulses.
You missed the point. If the amorphous film element has negative
temperature coefficient of resistance, it won't be damaged - it will
just form a hot channel and let lots of current through without
sustaining any permanent damage, though anything in series with it may >>>> not be as lucky. Once the hot channel cools down it will work just as it >>>> did before.
Multiple experiments consistently disagree.
Try it.
The experiment in about 1975 that I witnessed did not destroy the carbon
film resistor. It was carefully designed to show how hot channels
worked. A less expert experimenter might not have got the same result,
and a less receptive audience might not have understood what was being
demonstrated.
50-year old memories and droning insults are no substitute for recent experiments.
My little 5-watt surface-mount wirewounds are doing fine, pulsing at
60 amps, 3600 watts, 2 usec. That killed the Bourns 35 watt thickfilms overnight.
Sounds like you're not insulating the heat source.
?????
If so, then a soft copper foil introduced between the
device and an aluminum spreader works pretty well as
a gap filler and a conductive interface.
RL
Only if it flows enough to fill the gaps. That's unlikely with copper.
| Sysop: | Amessyroom |
|---|---|
| Location: | Fayetteville, NC |
| Users: | 70 |
| Nodes: | 6 (0 / 6) |
| Uptime: | 37:37:13 |
| Calls: | 948 |
| Calls today: | 2 |
| Files: | 1,325 |
| Messages: | 280,462 |
