From Newsgroup: sci.electronics.design

Basically, it doesn't work. It's cribbed off the internet. When I
connect a battery,( lipo) the output ( TP5) is always on.
R3/D2 is supposed to guarantee a switch off when the switch is pressed whilst the circuit is on.
This is a dropbox link but I'm not sure if it can be accessed by anyone

https://www.dropbox.com/scl/fi/7l0abaly8cyduatirbyc6/receiverswitch.jpg?rlkey=o7dilm4mopzcb4m4mtxmjfxfo&st=yqz4i6i9&dl=0
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From Newsgroup: sci.electronics.design

On 4/06/2026 1:17 am, Edward Rawde wrote:

"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10vp60g$3kkmu$1@dont-email.me...

On 3/06/2026 5:29 pm, TTman wrote:

On 03/06/2026 03:16, Bill Sloman wrote:

On 3/06/2026 10:33 am, Phil Hobbs wrote:

TTman <kraken.sankey@gmail.com> wrote:

Basically, it doesn't work. It's cribbed off the internet. When I
connect a battery,( lipo) the output ( TP5) is always on.
R3/D2 is supposed to guarantee a switch off when the switch is pressed >>>>>> whilst the circuit is on.
This is a dropbox link but I'm not sure if it can be accessed by anyone >>>>>>
https://www.dropbox.com/scl/fi/7l0abaly8cyduatirbyc6/ receiverswitch.jpg?rlkey=o7dilm4mopzcb4m4mtxmjfxfo&st=yqz4i6i9&dl=0

With a PFET, the source-drain diode conducts when the source is more >>>>> positive. You need to exchange drain and source.

Might be tricky. Most FETs are symmetrical, and for a P-FET the source is whichever of the source and drain connections that
happens to be more positive.

So I need to flip source and drain? I'll try that...

Don't bother. The FET decides which terminal is source or drain on the basis of the voltage at each connection.

In that case please explain why reversing the source and drain in the simulation
I posted results in a circuit which no longer works.

The simulation uses a defective model for the FET

Yes I know the explanation is obvious but you seem to be implying that the FET
will work either way in that circuit. This is incorrect so telling the OP not to bother
doing that is nonsense.

Why do you think that it is incorrect? The simulation isn't evidence of
what the actual part will do.

Phil gave the correct solution .
The only other thing I would note is the way the load characteristics may affect
operation but this is explained on the web page I posted.

Even asymmetrical FETs work that way, but the performance can vary a bit if the areas playing the role are bigger or smaller.

--
Bill Sloman, Sydney


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From Newsgroup: sci.electronics.design

On 6/2/2026 11:18 PM, Edward Rawde wrote:

"TTman" <kraken.sankey@gmail.com> wrote in message news:10vnl0a$38eli$1@dont-email.me...

Basically, it doesn't work. It's cribbed off the internet. When I connect a battery,( lipo) the output ( TP5) is always on.
R3/D2 is supposed to guarantee a switch off when the switch is pressed whilst the circuit is on.
This is a dropbox link but I'm not sure if it can be accessed by anyone

https://www.dropbox.com/scl/fi/7l0abaly8cyduatirbyc6/receiverswitch.jpg?rlkey=o7dilm4mopzcb4m4mtxmjfxfo&st=yqz4i6i9&dl=0

Phil was right first time and it won't work without a load (R4 in the simulation below).

This site has various variations of it. http://www.mosaic-industries.com/embedded-systems/microcontroller-projects/electronic-circuits/push-button-switch-turn-on/latching-toggle-power-switch

Nice - Thanks.
Ed

<snip>

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From Newsgroup: sci.electronics.design

So that we all know what FET we're talking about,
please assume the P-channel one in this package.

https://www.infineon.com/dgdl/irf7309pbf-1.pdf

You might also want to explain why the symbol includes a diode and
what that will do to the circuit if you reverse the FET.

Did you miss on my picture that the p fet is AO3047 and the n fet is
2n7002 ( both sot23).... I'm beginning to wonder if I need to use fets
with a low vGs The simulation works fine with the IRF dual part.
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From Newsgroup: sci.electronics.design

On 03/06/2026 16:53, Edward Rawde wrote:

"Jan Panteltje" <alien@comet.invalid> wrote in message news:10vofhf$3e4h1$1@dont-email.me...

TTman <kraken.sankey@gmail.com>wrote:

Basically, it doesn't work. It's cribbed off the internet. When I

connect a battery,( lipo) the output ( TP5) is always on.
R3/D2 is supposed to guarantee a switch off when the switch is pressed >>> whilst the circuit is on.
This is a dropbox link but I'm not sure if it can be accessed by anyone

https://www.dropbox.com/scl/fi/7l0abaly8cyduatirbyc6/receiverswitch.jpg?rlkey=o7dilm4mopzcb4m4mtxmjfxfo&st=yqz4i6i9&dl=0

If you are going to drive a microprocessor then let that do the on-off thing:
Like this one:
https://panteltje.nl/pub/SWR_bridge_display_and_acquision_working_IMG_5018.JPG

You want to use a microprocessor for a push on/off power switch?
I'd have to admit I know people who might.
And if there's already a processor in the system then maybe sometimes it makes sense.
The usual process is:
1. Connect the switch to an input port with a pull up resistor if necessary. 2. Write software which logically will work perfectly.
3. Have trouble understanding what is going wrong.
4. Discover switch bounce.

In the field that I'm looking at, all devices use a micro as it is the simplest solution to achieve the desired result. A polled push button
switch contact, whilst in deep sleep mode, is the obvious solution.The switches are invariable the 5mmx5mm tactile buttons that cost a couple
of pence ( compared to a toggle switch @-u1 plus.)
copule of options for me... try piglets on /hold off or consider a
latched push button.Try some low vGs fets... Downside is I already have
PCBs and I don't like to be beaten by something I don't really
understand- burried diodes? I spent 50+ years in the digital domain (
ever since RTL/DTL>TTL.) Analogue I just don't get :(
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From Newsgroup: sci.electronics.design

With the exception of PFET wiring error, just exchange D-S to fix it, that's a pretty good circuit. TR1 /TR2 form a classic bistable latch, meaning turn it on and it stays on, and turn it off and it stays off. The actuating signal via SW-PB is momentary. Taking ON to mean TR1 is on and passing Vbatt to the output, the state is latched by the Vbatt output through R3 to the gate of TR2 turning it on and pulling the gate of TR1 to GND, reinforcing the ON condition.
Cap is discharged to 0V in the ON state through R2 and the drain of TR2. So pressing SW-PB during the ON state causes the gate of TR2 to be discharged into the much larger 1u Cap. TR2 then turns off instantly, causing the gate of TR1 to be charged high through R1, turning TR1 off. Since Vbatt is removed from the output, the latching voltage through R3 is removed, and the gate of TR2 stays discharged, latching TR2/TR1 off. If you continue to hold the press on SW-PB, the gate of TR2 will be charged through R2 and R3/D2 to the output. The circuit will eventually go out of the OFF state and back to the ON state if Cap is allowed to charge to TR2 gate threshold. To prevent this, a loaded output limiting the Cap voltage to 0.2V will work. The series resistance is approximately R2= 100k, so Rmax, load= 0.2V/(Vbatt/100k)= 4.7kR should work. You can eliminate that 3/4 ma static loading in the ON state with another momentary, ganged to SW-PB. Or you can migrate to LVMOS logic for a bistable controlling the single AO3047, and have zero static loading in either state.
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