From Newsgroup: comp.misc

From the -2cool-+ department:
Feed: Ken Shirriff's blog
Title: Cores in space: The core memory module from a 1980 Spacelab
computer
Author: Ken Shirriff
Date: Sun, 30 Aug 2026 09:42:42 +0000
Link: http://www.righto.com/2026/08/spacelab-core-memory.html

Spacelab was a reusable laboratory that could be carried in the Space
Shuttle's cargo bay, providing lab space for astronauts and
experiments.1[1] Because Spacelab was a European project, it used a French-built minicomputer, the Mitra 125 MS,2[2] rather than the
Shuttle's main computers, IBM-built AP-101 systems. For storage, the
Spacelab computer contained 128 kilobytes of RAM. Rather than silicon
memory, the computer used magnetic core memory, with each bit stored in
a tiny ferrite ring. In this article, I take a close look at this
computer's core memory system.

[image 1: The core stack from the Spacelab computer. I removed the top
board to show the core planes. (link #4)][3]

The core stack from the Spacelab computer. I removed the top board to
show the core planes.

The illustration below shows how Spacelab fit inside the Shuttle's cargo
bay. The pressurized laboratory is the cylindrical module in the front
of the cargo bay, connected to the Shuttle by a tunnel. Experiments were mounted on pallets behind the laboratory. The laboratory held three
identical Mitra computers.3[5] One computer managed Spacelab itself,
while the second computer managed the experiments. The third computer
provided a backup in case of failures.

[image 2: Spacelab was a pressurized cylinder in the Shuttle's cargo
bay, connected to the Shuttle by a tunnel. It provided a laboratory for researchers to perform experiments. This illustration of Spacelab is
from NASA, C-1976-4380. (link #7)][6]

Spacelab was a pressurized cylinder in the Shuttle's cargo bay,
connected to the Shuttle by a tunnel. It provided a laboratory for
researchers to perform experiments. This illustration of Spacelab is
from NASA, C-1976-4380.

The photo below shows the core memory stack, removed from the computer.
The core memory stack takes up roughly a third of the computer. The
entire side panel of the computer detaches, and the core memory unit
slides out. Since the computer is cooled by conduction, firmly attaching
the core memory stack to the side panel kept it cool. The core memory
stack consists of seven boards: a driver board, four core plane boards,
a second driver board, and an interface board. Each board has two
160-pin connectors that plug into a large daughter board on each side, providing extensive connectivity between the boards. The daughter board
on the right has another 160-pin connector that links the memory stack
to the rest of the computer. (These connectors are the long blue
connectors in the photo.)

[image 3: The core memory stack in front of the Mitra computer. The
circuit boards have been removed from the far side of the computer.
(link #9)][8]

The core memory stack in front of the Mitra computer. The circuit boards
have been removed from the far side of the computer.

How core memory works

One of the hardest problems for early computers was storage. Computers
of the late 1940s and early 1950s stored data through techniques such as
sound waves in mercury, spots on a CRT screen, or spinning magnetic
drums, but these all had limitations. What computers needed was dense, inexpensive storage that was fast, reliable, and could be accessed
randomly.

During World War II, Germany developed special magnetic alloys[10] that
could "flip" from one magnetic state to another. After the war, American researchers realized that these materials could be used for storing
binary data: "It was completely obvious that you could make a memory
with this material," in the words of Jan Rajchman. Different aspects of
core memory were patented by various inventors (including independent
inventor Frederick Viehe, An Wang at Harvard, Jan Rajchman at RCA, and
Jay Forrester at MIT), leading to expensive patent battles. (IBM ended
up paying $400,000 to WangrCowho used the money to build the computer
company Wang LaboratoriesrCoand $13,000,000 to MIT.) I view Jay Forester
as the most important inventor, developing the design of practical core
memory, researching magnetic materials, and building the first core
memory in 1953 for the groundbreaking Whirlwind computer.

Core memory is based around a tiny toroidal magnetic core, one per
bit.4[11] A core can be magnetized clockwise or counterclockwise to
store a bit. The core can be magnetized by threading a wire through the
core: running a current through the wire produces a magnetic field that magnetizes the core, while running a current in the opposite direction
produces the opposite magnetization.

A key problem with core memory was how to wire the cores without an
absurd number of wires: if each core had a separate wire, just 16 KB of
storage would require over 100,000 wires. The solution was called
"coincident current addressing". The cores are arranged in a grid, with horizontal and vertical wires, as shown below. By running a current
through one horizontal wire and one vertical wire, the single core at
the intersection was selected. But wouldn't that magnetize all the cores
along the horizontal and vertical wires? The key was that the cores were constructed from special magnetic materials with a property called
hysteresis: a small current leaves the core completely unchanged, while
a larger current flips the core's magnetic state. The currents through
the horizontal and vertical wires were carefully selected so each wire
had half the current necessary to flip the core; where the wires
intersected, the two currents provided sufficient magnetic field to flip
the core.

[image 4: Energizing an X drive wire and a Y drive wire selects one
core, highlighted in yellow. Diagram adapted from Digital Computer
Components and Circuits, R. K. Richards, p355 (link #13)][12]

Energizing an X drive wire and a Y drive wire selects one core,
highlighted in yellow. Diagram adapted from Digital Computer Components
and Circuits[14], R. K. Richards, p355

The next step was reading the core. A sense wire was threaded through
all the cores in the two-dimensional plane. To read a core, the X and Y
select wires were driven to flip the desired core to the 0 state. If the
core was already in the 0 state, nothing happened. But if the core was originally in the 1 state, the magnetic field changed as the core
changed state. This induced a small current in the sense line,
indicating that the core held a 1. Note that reading the value of a bit destroys that value. Thus, a core needs to be rewritten after reading,
to restore the original data.

To access a word of memory at a time, core planes were combined into a three-dimensional stack (below). Since each plane held one bit of the
word, a 16-bit word would have a stack of 16 planes. All the planes
shared the signals to drive the X and Y lines, so a one-word column
through the stack was accessed in parallel. Each plane had a separate
sense line to read out the bit.

[image 5: The core stack from the Saturn V LVDC (Launch Vehicle Digital Computer) consists of 14 core planes. This stack is at the US Space &
Rocket Center. Photo from NCAR EOL. I retouched the photo to reduce
distortion from the plastic case. (link #16)][15]

The core stack from the Saturn V LVDC (Launch Vehicle Digital Computer) consists of 14 core planes. This stack is at the US Space & Rocket
Center. Photo from NCAR EOL[17]. I retouched the photo to reduce
distortion from the plastic case.

But how do you write different values to the different bits? The trick
was to put an "inhibit" line through all the cores in a plane, running
the inhibit line in the opposite direction to the X lines. Putting a
current through the inhibit line would cancel out the current through
the X line, preventing the core in that plane from being modified. To summarize, a read-write cycle consisted of first energizing a pair of X
and Y lines to select a word and write a 0 to the column of cores in
that word. The sense lines provided a readout of the bit values. Next,
the X and Y lines were energized in the opposite direction to write a 1
to the cores. At the same time, the inhibit lines were energized for
each plane with a 0 bit. Thus, the cores either flipped back to 1 or
stayed at 0, as required. Many core memories, such as the one below,
used a shared wire for sense and inhibit, so there were three wires
through each core.

[image 6: Closeup of an IBM 360 Model 50 core plane. The cores in this
computer were called 19-32 because their inner diameter was 19 mils and
their outer diameter was 32 mils (0.8 mm). (link #19)][18]

Closeup of an IBM 360 Model 50 core plane. The cores in this computer
were called 19-32 because their inner diameter was 19 mils and their
outer diameter was 32 mils (0.8 mm).

The final ingredient to make core memory practical was the diode matrix.
The X and Y lines require driver circuits that can produce fast,
bidirectional high-current (e.g. 600 mA) pulses. A core memory plane can
have hundreds of these lines. Providing a separate driver for each wire
would be very expensive, especially in the vacuum tube era. The solution
was to put separate drivers at each end of the wire, with each driver supporting multiple wires. For a trivial example, suppose you have 9
vertical lines. Put three drivers (A, B, and C) on the top, each
connected to three wires, and three drivers on the bottom (1, 2, and 3),
each connected to three wires. By energizing a driver at the top and a
driver at the bottom (e.g. B and 1), the corresponding wire will be
energized. Now, N drivers on each side control N^2 wires, supporting N^4
cores in total.

[image 7: Illustration of how "top" and "bottom" drivers work together
to select a single line (red) through the core matrix. However, current
can take alternate paths, such as the pink path. (link #21)][20]

Illustration of how "top" and "bottom" drivers work together to select a
single line (red) through the core matrix. However, current can take
alternate paths, such as the pink path.

Unfortunately, it's not quite that easy. Current can take "sneak paths"
through the cores, such as the path in pink above. The solution is to
add diodes to ensure that current can't take the wrong path. Since a
wire needs to be driven with currents in both directions (to flip cores
both ways), two diodes are required on each wire, as shown below, one in
each direction. Each matrix input (A, B, etc.) is replaced with two
inputs, one to drive each direction. (The horizontal wires also require
diodes, not shown.)

[image 8: Adding diodes ensures that current only takes the desired
path. (link #23)][22]

Adding diodes ensures that current only takes the desired path.

Since each wire requires two diodes, core memories used many diodes. Fortunately, diodes were small and inexpensive, so a large quantity of
diodes was manageable. The photo below shows the diode stack for the
computer used in the Saturn V rocket, the Launch Vehicle Digital
Computer.

[image 9: Closeup of the diode matrix in the Saturn V LVDC. Diodes are
mounted vertically using cordwood construction between two printed
circuit boards. (link #25)][24]

Closeup of the diode matrix in the Saturn V LVDC. Diodes are mounted
vertically using cordwood construction between two printed circuit
boards.

Originally, core memories were tediously constructed by hand. For the
Whirlwind computer, it took a full 40 hours to wire a 64|u64 core plane. Companies such as IBM soon developed automated techniques to manufacture
core memory, and the price dropped by a factor of two every two years,
similar to Moore's Law.5[26] Core memories became fast, inexpensive, and reliable, and were the most popular form of main-memory storage until semiconductor memory took over in the 1970s.

The Spacelab computer's core memory

The Spacelab computer's memory was manufactured in 1980, a late date for
core memory, so it is advanced and high density. The photo below shows
one of the four core plane boards from the computer. Each board holds
16K of 18-bit words (32 KB), so the computer has 128 KB of RAM in total.
The computer is a 16-bit computer, but each word also has a parity bit
and a "storage protect" bit, bringing the total to 18 bits. (The storage protect bit provided write protection on a word-by-word basis,
preventing programs from being accidentally overwritten. Because core
memory is nonvolatile, a program could be loaded into memory once and
would be immediately available every time the computer was powered on.)

[image 10: One of the core memory boards from the Spacelab computer.
(link #28)][27]

One of the core memory boards from the Spacelab computer.

The core memory board is arranged with 1024 vertical (Y) wires and 288 horizontal (X) wires, supporting 294,912 lithium ferrite cores. These
very thin wires are soldered to tiny pads on the printed-circuit board.
The board supports 18 bits, which is visible as 18 alternating stripes
of green and copper because alternating sense lines have different
colors. The board has 36 sense lines: the left and right halves of the
board have independent sense lines to reduce noise, so the board has 36
sense lines for 18 bits. The sense wires pass through four holes in the
board (green arrows) and are soldered on the back of the board.

The photo below shows a close-up of the cores. Each core is
approximately 32 mils (0.8mm) in diameter, the same as the IBM
System/360 cores shown earlier. However, the cores are stacked much
closer, with only a small gap between cores. The X and Y select lines
are copper-colored, while the sense lines are green. (The wires are all enameled to prevent short circuits.) The sense wires loop around at the
left, forming a single circuit through each bit section. Half the Y
lines form loops at the bottom; the other half form loops at the top.
Thus, each Y line passes through the plane twice in a U-shaped path,
which will turn out to be important.

[image 11: A close-up of the cores. I think that some rows tilt left and
some tilt right to ensure that the sense lines keep the same polarity
when they switch direction. Photo courtesy of CuriousMarc. (link
#30)][29]

A close-up of the cores. I think that some rows tilt left and some tilt
right to ensure that the sense lines keep the same polarity when they
switch direction. Photo courtesy of CuriousMarc.

The other side of each circuit board holds the sense amplifiers and the
diode matrix for the core plane. The diode chips are the square black
packages, each containing 16 diodes for 8 core lines.6[31] In the
red-outlined regions, one end of each vertical U-loop is connected to a
diode chip; the lines of diagonal holes are the vias that pass each
signal through the board. The other end of each vertical U-loop is
connected to one of the blue board connectors on the side; these vias
are in the blue-outlined regions. The horizontal lines use the diode
chips and vias in the green regions. One end of each line is connected
to a diode chip, while the other end is connected to a board connector
through traces on the other side. Note that some vertical lines connect
to the diode chips at the top of the board, while others connect at the
bottom. Similarly, some horizontal lines connect at the left while
others connect at the right.

[image 12: The back side of the core plane board holds the diode
matrices and sense amplifiers. (link #33)][32]

The back side of the core plane board holds the diode matrices and sense amplifiers.

The central region (yellow) holds 18 sense amplifier chips, the black
DIP integrated circuits, each containing two amplifiers.7[34] The white packages are resistor packages, holding multiple resistors to bias and terminate the sense amplifier lines. The wires from the sense amplifiers
are connected as twisted pairs that are soldered to the board right next
to the corresponding sense amplifier chips. Using twisted pairs for the
whole distance prevents the wires from picking up electrical noise,
which could overwhelm the tiny signals in the sense wires. The sense
wires pass from one side of the board to the other through four holes in
the board (yellow arrows), and then are glued down as they traverse a significant distance on the board. (It must have been difficult to
manufacture the board without breaking the tiny, fragile wires.)

[image 13: Each sense wire loop forms a twisted pair that is fed to the
other side through a hole in the circuit board. Above the hole, you can
see a gray blob whereN++sense wires were spliced for some reason.N++Also
note how alternating vertical wires are soldered to theN++circuit board,
with circular vias connected to the other side. The other vertical wires
form loops.N++are soldered to the circuit board (link #36)][35]

Each sense wire loop forms a twisted pair that is fed to the other side
through a hole in the circuit board. Above the hole, you can see a gray
blob where sense wires were spliced for some reason. Also note how
alternating vertical wires are soldered to the circuit board, with
circular vias connected to the other side. The other vertical wires form
loops. are soldered to the circuit board

Detecting signals on the sense lines is tricky because the pulses are
very small, a few millivolts. Because the sense lines run next to the X
drive lines, they can easily pick up noise from the high-current pulses
on the X lines. To minimize this noise, the sense lines cross each other between two plane sections, forming a "bow tie", as shown below. The
result is that an X line runs next to the positive sense line for half
the length and the negative sense line for the other half. Thus, the
induced noise cancels out.

[image 14: A close-up of the sense lines. The 16 sense lines in the
middle are green, while the sense lines above and below (as well as the
X lines) are copper. Note that the sense lines cross, while the X lines continue horizontally. The large circles are vias through the board.
(link #38)][37]

A close-up of the sense lines. The 16 sense lines in the middle are
green, while the sense lines above and below (as well as the X lines)
are copper. Note that the sense lines cross, while the X lines continue horizontally. The large circles are vias through the board.

The core memory in the Spacelab computer used a different architecture
from a typical core memory, improving performance by eliminating the
inhibit line. This architecture was called a 2-+D memory.8[39] If you're familiar with core memory, the lack of inhibit lines may seem puzzling:
how do you write 1 to some bits and 0 to other bits? The trick is to
have separate X driver circuitry for each bit.9[40] When writing data,
the X lines are only energized for bits that receive a 1; the other
lines are left unenergized, so the bits remain at 0. The disadvantage is
that instead of one set of X driver circuits, you now need one set for
each bit, a factor of 18 more for an 18-bit word. However, with the
development of core drivers on integrated circuits, the cost of the
additional driver circuitry became less significant.

The memory system used an technique called phase reversal to cut the
number of vertical drivers in half. Recall that pairs of vertical wires
are joined by a U-connection. By driving the wire in a particular
direction, the left side or the right side of the pair can be selected.
For example, the drawing below shows how the two wires select the left
core, but not the right core. In the left core, both currents go through
the core in the same direction, inducing a magnetic field in the
toroid.10[41] But in the right core, the two currents cancel out, so
there is no magnetic field created. But if the current in the vertical
loop is reversed, the right core will be selected, rather than the left
core. The point is that instead of using two drivers for the vertical
wires, one driver is used, reversing the current to select the left or
right core.

[image 15: Connecting pairs of vertical wires into a U-shaped loop lets
each driver control twice as many cores. (link #43)][42]

Connecting pairs of vertical wires into a U-shaped loop lets each driver control twice as many cores.

The diagram below shows the complex wiring for X drive wires. Each band
of 16 wires corresponds to one bit in the 18-bit word, and has a
separate sense wire. The top band of 16 X lines is connected to four
contacts on the board connector; each contact is connected to four X
lines through the curving PCB traces. The bottom band of 16 X lines is
wired to diode modules on the other side of the board, connected through
the round vias. (Each wire has the opposite connectionsrCodiode module or
board connectorrCoon the other end.)11[44] One group of four X wires is energized through the connector, while four wires are energized through
the diode matrix, selecting one of the 16 X wires in the group.

[image 16: The PCB wiring for the X lines. (link #46)][45]

The PCB wiring for the X lines.

Other boards in the memory stack

The memory stack has seven boards in total, arranged as a driver board,
the four core planes, a second driver board, and an interface board. I
haven't examined these boards in detail, but I'll give some preliminary information. The photo below shows one of the two driver boards. It
provides the high-current pulses for the X and Y select lines. The board
is crammed with specialized core memory driver chips12[47], along with a
few logic chips to control the drivers. It has separate drivers for the
two ends of the select lines, allowing the matrix selection described
earlier.

[image 17: One of the two memory driver boards. Click this image (or any
other) for a larger version. (link #49)][48]

One of the two memory driver boards. Click this image (or any other) for
a larger version.

Since there are two driver boards and four core memory boards, at first
I thought that each driver board controlled two core memory boards. The configuration turns out to be more complicated, with one more layer of
matrix selections to cut the number of drivers in half. To simplify
slightly, consider the X lines on a core board to have left ends and
right ends, both of which must be energized to activate a line. For the
left ends, the first driver board powers core boards 1 and 2, while the
second driver board powers core boards 3 and 4. The right ends are
shuffled: the first driver board powers core boards 1 and 3, while the
second driver board powers core boards 2 and 4. Now, if the first driver
board powers the left and right ends, core board 1 is the only one with
both ends active. If the first driver board powers the left ends while
the second board powers the right ends, core board 2 is activated.
Similarly, core board 3 or 4 can be activated. The point is that since
each set of drivers is connected to two core boards, two sets of drivers
are required instead of four.

The final board is the interface to the rest of the computer. It has
many transistor arrays in DIP packages, along with many resistors. It
seems that the board uses discrete transistors to drive the bus, rather
than using interface chips, which is unexpected. The board has some wire-wrapped jumpers in the lower center region, presumably for
configuration.

[image 18: The interface board has some unused space in the lower left.
(link #51)][50]

The interface board has some unused space in the lower left.

Conclusions

Core memory had a long life, surviving even as computers migrated from
vacuum tubes to transistors and then integrated circuits, but eventually semiconductor memory made it obsolete.13[52] Core memories lasted even
longer in aerospace applications since it had two key advantages over semiconductor memory: it retained data even without power, and it was
resistant to radiation. The Spacelab computer, manufactured in 1980, was
near the end of core memory's reign, so it is more advanced than a
typical core memory system, with higher density, extensive use of
integrated circuits, and the 2-+D architecture. But eventually the high density, low cost, and low power consumption of semiconductor memory won
out. In 1991, the Space Shuttle flew with upgraded main computers, the
IBM AP-101S that used semiconductor memory instead of magnetic core.
Spacelab's Mitra computers were also replaced, using the AP-101SL, which
was based on the AP-101S but modified to support the instruction set and peripherals of the original Spacelab computer.14[53] Although core
memory is now firmly in the past, it still lives on in the expression
"core dump".

I plan to investigate the Spacelab computer some more. For updates,
follow me on Bluesky (@righto.com[54]), Mastodon (@kenshirriff@oldbytes.space[55]), or RSS[56]. Credits: Thanks to Steve Jurvetson for providing the Spacelab computer. Thanks to CuriousMarc[57]
for photography and help disassembling the computer. AI statement:
Despite the presence of the em dash, no AI was used in the writing of
this article (details[58]).

Notes and references


1.

It seems that 16[59] Shuttle flights used the Spacelab pressurized
module, while 6[60] or 9[61] flights just used the unpressurized
Spacelab pallets. (Why do sources never agree?) Originally, Spacelab
was expected to be used for 30 flights every year (Status Of The
Spacelab Program[62], 1974). ra-[63]
2.

The Spacelab 125 MS computer was built by a French company called
CIMSA, using the Mitra architecture created by CII. I explained the
complex history of these companies in my previous Spacelab computer article[64], so I won't go into it here.

On the ground, the Spacelab project used Mitra 125 S computers that
were functionally identical to the Mitra 125 MS (details[65])
computers that were used in space. A core memory board from a Mitra
125 S ground computer was described on EEVblog (video[66],
video[67]). The computers had identical architectures, but the 125
MS was militarized and designed for "severe environmental
conditions" (details[65]). The EEVblog memory board was manufactured
by Ampex and has a different design from the board that I examined.

[image 19: The Mitra 125 S memory board, built by Ampex. Screenshot
from EEVblog #668. (link #69)][68]

The Mitra 125 S memory board, built by Ampex. Screenshot from
EEVblog #668[70].

-ara-[71]
3.

Spacelab was modular, so it could be be flown in different
configurations. The habitable module could be flown in two different
sizes, with experiment pallets mounted outside the module. Spacelab
could also be flown without the habitable module, with experiments
controlled from inside the Shuttle. In this case, the computers and
other equipment were mounted in a smaller pressurized cylider called
the "igloo". ra-[72]
4.

I'm describing "standard" core memory, but there were many esoteric
designs for core memory. One approach used two cores per bit.
Another approach used cores with multiple holes, such as cubical
BIAX[73] cores, transfluxors[74] with a large hole and a small hole,
or IBM's three-hole design. Many of these approaches could read a
core without erasing it (non-destructive readout), but almost all
cores used standard toroids. ra-[75]
5.

Later, companies discovered that it was cheaper to have core
memories hand-manufactured in Asia and moved away from automated
production. (See Memories that Shaped an Industry[76], p. 251. If
you're interested in the history of core memory, this is the book to
read.) ra-[77]
6.

The diode array chip is marked FSA2977 and contains 16 diodes, 8
common-cathode and 8-common anode. Pins 2 through 9 are connected to
eight core wires. Pin 1 is driven high, or pin 10 is driven low,
depending on the desired current direction. I couldn't find a
datasheet for this part, but it appears to be similar to the
Motorola MAD1103 Core-Driver Diode Array or the Silicon General
SG5772F[78].

ra-[79][image 20: A schematic matching the diode array, from the
Motorola MC1103P datasheet. (link #81)][80]

A schematic matching the diode array, from the Motorola MC1103P
datasheet[82].
7.

The sense amplifiers are National Semiconductor DS5534 chips. Each
IC contains two differential amplifiers, converting the tiny sense
signals into logic signals. The strobe signals indicate when the amp
should read a bit; the strobes come from the IC on the left side of
the board, a 54150 dual 4-input NAND gate, 50+- line driver.

[image 21: Diagram of the sense amplifier, from the National
Interface Integrated Circuits Databook. (link #84)][83]

Diagram of the sense amplifier, from the National Interface
Integrated Circuits Databook[85].

-ara-[86]
8.

The 2-+D memory architecture is described in detail in 2 1/2 D High
Speed Memory SystemsrCoPast, Present, and Future[87]. Due to
complicated factors and tradeoffs, the 2-+D approach was attractive
for systems of 16 Kword storage and above. In particular,
eliminating the inhibit line boosted performance. IBM's Large
Capacity Storage[88] system used a 2-+D architecture with just two
wires per core to provide a megabyte of storage at a comparatively
low cost, sharing the X line with the sense line. However, this
approach turned out to be slow, so using three wires per core (as in
the Spacelab computer) was more common. ra-[89]
9.

Note that the 2-+D architecture requires separate per-bit drivers
along one axis, not both. Since cores require two currents to flip, inactivating one axis is enough to prevent the corresponding cores
from flipping. ra-[90]
10.

The direction of the magnetic field is given by the "right-hand
rule[91]": if you point the thumb of your right hand in the
direction of the current, the magnetic field curves around the wire
in the direction of your fingers.

It may not be obvious how the currents add or cancel when the wires
are in different directions. You can imagine moving the two wires
until they are parallel, and then see if the currents are in the
same direction or opposite. (This follows from Amp|?re's law[92],
which states that the magnetic field around a curve (e.g. the core)
is proportional to the net current through the corresponding
surface.) ra-[93]
11.

For reference, this footnote describes the details of the core plane
wiring, probably in more detail than anyone wants. For the Y lines,
there are 1024 vertical lines, forming 512 U-shaped loops. Half of
these are connected at the top, and half at the bottom. One end of
each loop is wired directly to a connector on the side, while the
other end connects to a diode matrix. The connectors provide 32
lines that can act as a source or a sink. Each of the 32 lines is
connected to 16 vertical wires, for 512 vertical wires in total.
Each quadrant of the board has 8 of the 32 lines, connected to a
group of 8 vertical wires, a second group of 8 vertical wires, and
so forth for 16 groups.

For the diode connections, the connectors provide 16 source lines
and 16 sink lines. Each diode chip has one source line and one sink
line, feeding 8 vertical wires. Each source and sink line is
connected to four diode chips, one in each quadrant in a mirrored
pattern. Thus, the 16 source lines and 16 sink lines are connected
to 64 diode chips, feeding 512 vertical loops. (Since each quadrant
of the board has unique direct connections and the diode connections
within a quadrant are unique, a unique core is selected.
Specifically, 32 direct connections times 16 diode connections gives
512 combinations to select a vertical loop. The polarity selects
which half of the loop is active, uniquely selecting one of 1024
vertical wires.)

For the horizontal wiring, the 288 wires are grouped into 18 bands
(one for each bit), with 16 wires per band. Each band has four
direct signals from the connector. Each one is connected to four
horizontal lines, 16 in total. (The visible PCB traces (shown
earlier) connect the 16 wires to four connector pins (A,B,C,D) in
the pattern AABBCCDDDDCCBBAA.)

For the horizontal diode connections, the connector provides 4
source wires and 4 sink wires, which feed the 16 horizontal wires in
a pattern 1234123412341234. By energizing the appropriate direct and
diode wires on either side, one of the 16 lines is selected. One
complication is that each diode chip has 8 outputs, but each
source/sink goes to 4 wires. The solution is that each bit group
uses half of four diode chips (4 outputs from each). Thus, the four
source and sink wires are shared across two bit groups. This is not
a problem for selection because the direct connections control
whether the bit is active or not.

The horizontal diodes are arranged asymmetrically. The left side has
8 diode chips at the top and 8 at the bottom, supporting 8 groups of
16 wires. The right side has 20 diode chips (4 additional in the
middle), supporting 10 groups of 16 wires. Thus, all 18 bit groups
are supported, with some asymmetry in the board layout.

The left and right sides of the core plane have separate sense
lines, so there are 36 sense lines in total. These go to the 18 dual
sense amplifiers. Each sense amplifier has two outputs connected, a
wired-OR to combine the left-hand data with the right-hand data,
providing 18 bits of output to the connector.

[image 22: A diagram showing the topology of a core board. Click
this image (or any other) for a larger version.) (link #95)][94]

A diagram showing the topology of a core board. Click this image (or
any other) for a larger version.)

The diagram above summarizes the structure, showing one of the 18
bits. It omits the details of which connections are at the top,
bottom, left, or right. ra-[96]
12.

Each driver board has 53 core driver chips of type SN55325[97].

[image 23: The SN55325 core driver chip, from the databook. (link
#99)][98]

The SN55325 core driver chip, from the databook[97].

Each chip has two 600 mA "sources" and two 600 mA "sinks" connected
to two outputs. By energizing a source on one end of a line and a
sink on the other end, the line can be driven in the desired
direction. The driver board also has 39 driver chips of type
SN55327. These chips are similar, except they can be used as either
four sources or two sinks. These chips are used for the diode matrix
inputs, where an input is either a source or a sink. ra-[100]
13.

I wrote about the Spacelab computer's CPU earlier[64]. I've written
about other core memory systems including the IBM 1401 core
memory[101], IBM 360 core memory[102], Saturn V LVDC[103], and
Apollo Guidance Computer[104]. ra-[105]
14.

The Space Shuttle's replacement AP-101S computer used semiconductor
memory, so it needed to deal with volatility and radiation. The new
computer used battery backup to preserve memory contents when
powered off, a feature that core memory had provided automatically.
To avoid data corruption from radiation, the new computer had six
extra storage bits for each word to implement an error-correcting
code. The computer constantly scanned for bit errors and corrected
them. Radiation wasn't just a theoretical risk: a single Shuttle
flight could encounter over 100 bit flips due to radiation
(details[106]).

For more information on the AP-101S computer, see my previous
article, The rise and fall of IBM's 4 Pi aerospace computers[107]. I
wrote about Spacelab's original computer and the upgraded AP-101SL
computer in Reverse engineering circuitry in a Spacelab computer
from 1980[64]. ra-[108]


Links:
[1]: http://www.righto.com/2026/08/spacelab-core-memory.html#fn:spacelab (link) [2]: http://www.righto.com/2026/08/spacelab-core-memory.html#fn:ground (link) [3]: https://static.righto.com/images/cimsa-memory/core-stack.jpg (link)
[4]: https://static.righto.com/images/cimsa-memory/core-stack-w600.jpg (image) [5]: http://www.righto.com/2026/08/spacelab-core-memory.html#fn:modular (link) [6]: https://static.righto.com/images/cimsa-memory/spacelab.jpg (link)
[7]: https://static.righto.com/images/cimsa-memory/spacelab-w600.jpg (image) [8]: https://static.righto.com/images/cimsa-memory/computer-and-memory.jpg (link)
[9]: https://static.righto.com/images/cimsa-memory/computer-and-memory-w500.jpg (image)
[10]: https://spectrum.ieee.org/the-vacuum-tubes-forgotten-rival (link)
[11]: http://www.righto.com/2026/08/spacelab-core-memory.html#fn:esoteric (link)
[12]: https://static.righto.com/images/cimsa-memory/core-diagram.jpg (link) [13]: https://static.righto.com/images/cimsa-memory/core-diagram-w350.jpg (image)
[14]: https://archive.org/details/digital_computer_components_and_circuits/page/n183/mode/1up (link)
[15]: https://static.righto.com/images/cimsa-memory/lvdc-core-stack.jpg (link) [16]: https://static.righto.com/images/cimsa-memory/lvdc-core-stack-w500.jpg (image)
[17]: https://www.eol.ucar.edu/content/alabama-sightseeing-images (link)
[18]: https://static.righto.com/images/cimsa-memory/core-closeup2.jpg (link) [19]: https://static.righto.com/images/cimsa-memory/core-closeup2-w500.jpg (image)
[20]: https://static.righto.com/images/cimsa-memory/matrix.jpg (link)
[21]: https://static.righto.com/images/cimsa-memory/matrix-w300.jpg (image) [22]: https://static.righto.com/images/cimsa-memory/matrix-diodes.jpg (link) [23]: https://static.righto.com/images/cimsa-memory/matrix-diodes-w300.jpg (image)
[24]: https://static.righto.com/images/cimsa-memory/diode-board-x.jpg (link) [25]: https://static.righto.com/images/cimsa-memory/diode-board-x-w500.jpg (image)
[26]: http://www.righto.com/2026/08/spacelab-core-memory.html#fn:automated (link)
[27]: https://static.righto.com/images/cimsa-memory/core-board-labeled.jpg (link)
[28]: https://static.righto.com/images/cimsa-memory/core-board-labeled-w700.jpg (image)
[29]: https://static.righto.com/images/cimsa-memory/core-closeup.jpg (link) [30]: https://static.righto.com/images/cimsa-memory/core-closeup-w500.jpg (image)
[31]: http://www.righto.com/2026/08/spacelab-core-memory.html#fn:diodes (link) [32]: https://static.righto.com/images/cimsa-memory/matrix-board-labeled.jpg (link)
[33]: https://static.righto.com/images/cimsa-memory/matrix-board-labeled-w700.jpg (image)
[34]: http://www.righto.com/2026/08/spacelab-core-memory.html#fn:senseamp (link)
[35]: https://static.righto.com/images/cimsa-memory/sense-wires.jpg (link) [36]: https://static.righto.com/images/cimsa-memory/sense-wires-w400.jpg (image)
[37]: https://static.righto.com/images/cimsa-memory/sense-crossing.jpg (link) [38]: https://static.righto.com/images/cimsa-memory/sense-crossing-w500.jpg (image)
[39]: http://www.righto.com/2026/08/spacelab-core-memory.html#fn:2.5D (link) [40]: http://www.righto.com/2026/08/spacelab-core-memory.html#fn:axis (link) [41]: http://www.righto.com/2026/08/spacelab-core-memory.html#fn:right-hand-rule (link)
[42]: https://static.righto.com/images/cimsa-memory/core-angles2.jpg (link) [43]: https://static.righto.com/images/cimsa-memory/core-angles2-w300.jpg (image)
[44]: http://www.righto.com/2026/08/spacelab-core-memory.html#fn:details (link) [45]: https://static.righto.com/images/cimsa-memory/x-connections.jpg (link) [46]: https://static.righto.com/images/cimsa-memory/x-connections-w600.jpg (image)
[47]: http://www.righto.com/2026/08/spacelab-core-memory.html#fn:drivers (link) [48]: https://static.righto.com/images/cimsa-memory/driver-board.jpg (link) [49]: https://static.righto.com/images/cimsa-memory/driver-board-w600.jpg (image)
[50]: https://static.righto.com/images/cimsa-memory/interface-HMCL.jpg (link) [51]: https://static.righto.com/images/cimsa-memory/interface-HMCL-w600.jpg (image)
[52]: http://www.righto.com/2026/08/spacelab-core-memory.html#fn:core-articles (link)
[53]: http://www.righto.com/2026/08/spacelab-core-memory.html#fn:ap-101s (link) [54]: https://bsky.app/profile/righto.com (link)
[55]: https://oldbytes.space/@kenshirriff (link)
[56]: http://www.righto.com/feeds/posts/default (link)
[57]: https://www.youtube.com/curiousmarc (link)
[58]: https://www.righto.com/p/index.html#ai (link)
[59]: https://airandspace.si.edu/collection-objects/spacelab-laboratory-module/nasm_A19990001000 (link)
[60]: https://www.esa.int/About_Us/50_years_of_ESA/Spacelab-1_40_years_on (link)
[61]: https://www.britannica.com/topic/Spacelab (link)
[62]: https://commons.erau.edu/cgi/viewcontent.cgi?article=2820&context=space-congress-proceedings (link)
[63]: http://www.righto.com/2026/08/spacelab-core-memory.html#fnref:spacelab (link)
[64]: https://www.righto.com/2026/05/reverse-engineering-spacelab-computer.html (link)
[65]: https://ntrs.nasa.gov/api/citations/19790007875/downloads/19790007875.pdf#page=266 (link)
[66]: https://youtu.be/oJbgcbedHhI?si=nfj9DFGlKb_l-BkX&t=1618 (link)
[67]: https://youtu.be/oJbgcbedHhI?t=1629 (link)
[68]: https://static.righto.com/images/cimsa-memory/eevblog.jpg (link)
[69]: https://static.righto.com/images/cimsa-memory/eevblog-w500.jpg (image) [70]: https://youtu.be/oJbgcbedHhI?t=2278 (link)
[71]: http://www.righto.com/2026/08/spacelab-core-memory.html#fnref:ground (link)
[72]: http://www.righto.com/2026/08/spacelab-core-memory.html#fnref:modular (link)
[73]: https://www.computerhistory.org/revolution/memory-storage/8/253/984 (link)
[74]: https://www.righto.com/2024/02/the-first-microcomputer-transfluxor.html (link)
[75]: http://www.righto.com/2026/08/spacelab-core-memory.html#fnref:esoteric (link)
[76]: https://amzn.to/4yaPedW (link)
[77]: http://www.righto.com/2026/08/spacelab-core-memory.html#fnref:automated (link)
[78]: https://archive.org/details/bitsavers_siliconGenliconGeneralProductCatalog_43940822/page/n494/mode/1up (link)
[79]: http://www.righto.com/2026/08/spacelab-core-memory.html#fnref:diodes (link)
[80]: https://static.righto.com/images/cimsa-memory/diode-array.jpg (link) [81]: https://static.righto.com/images/cimsa-memory/diode-array-w250.jpg (image)
[82]: https://www.electronicsurplus.com/motorola-inc-mc1103p-core-driver-diode-array (link)
[83]: https://static.righto.com/images/cimsa-memory/sense-amp.jpg (link)
[84]: https://static.righto.com/images/cimsa-memory/sense-amp-w280.jpg (image) [85]: https://bitsavers.org/components/national/_dataBooks/1975_National_Interface_Integrated_Circuits.pdf#page=264 (link)
[86]: http://www.righto.com/2026/08/spacelab-core-memory.html#fnref:senseamp (link)
[87]: https://ieeexplore.ieee.org/document/4038821 (link)
[88]: https://en.wikipedia.org/wiki/IBM_2361_Large_Capacity_Storage (link) [89]: http://www.righto.com/2026/08/spacelab-core-memory.html#fnref:2.5D (link) [90]: http://www.righto.com/2026/08/spacelab-core-memory.html#fnref:axis (link) [91]: https://en.wikipedia.org/wiki/Right-hand_rule#Amp%C3%A8re's_right-hand_grip_rule (link)
[92]: https://en.wikipedia.org/wiki/Amp%C3%A8re%27s_circuital_law (link)
[93]: http://www.righto.com/2026/08/spacelab-core-memory.html#fnref:right-hand-rule (link)
[94]: https://static.righto.com/images/cimsa-memory/overall-topology.jpg (link) [95]: https://static.righto.com/images/cimsa-memory/overall-topology-w500.jpg (image)
[96]: http://www.righto.com/2026/08/spacelab-core-memory.html#fnref:details (link)
[97]: http://bitsavers.informatik.uni-stuttgart.de/components/ti/_dataBooks/1977_TI_Memory_Interface_Data_Book.pdf#page=199 (link)
[98]: https://static.righto.com/images/cimsa-memory/SN55325.jpg (link)
[99]: https://static.righto.com/images/cimsa-memory/SN55325-w300.jpg (image) [100]: http://www.righto.com/2026/08/spacelab-core-memory.html#fnref:drivers (link)
[101]: https://www.righto.com/2015/08/examining-core-memory-module-inside.html (link)
[102]: https://www.righto.com/2019/04/a-look-at-ibm-s360-core-memory-in-1960s.html (link)
[103]: https://www.righto.com/2020/03/the-core-memory-inside-saturn-v-rockets.html (link)
[104]: https://www.righto.com/2019/01/inside-apollo-guidance-computers-core.html (link)
[105]: http://www.righto.com/2026/08/spacelab-core-memory.html#fnref:core-articles (link)
[106]: https://klabs.org/DEI/Processor/shuttle/oneill_94.pdf (link)
[107]: https://www.righto.com/2026/03/ibm-4-pi-computer-history.html (link) [108]: http://www.righto.com/2026/08/spacelab-core-memory.html#fnref:ap-101s (link)

--- Synchronet 3.22a-Linux NewsLink 1.2