From Newsgroup: comp.lang.vhdl

I am trying to implement mod 6 counter using mod 8 counter with JK Flipflop but the output waveform is not correct as required.What is the mistake in my code?
module mod_six_counter(clk,rst,q,qbar);
input clk;
input wire rst;
output wire [2:0]q;
output [2:0]qbar;
assign rst = ~((~qbar[0])&qbar[1]&(qbar[2]));
jkff ff1(1'b1,1'b1,clk,rst,q[0],qbar[0]);
jkff ff2(1'b1,1'b1,qbar[0],rst,q[1],qbar[1]);
jkff ff3(1'b1,1'b1,qbar[1],rst,q[2],qbar[2]);
endmodule
module jkff(j,k,clk,rst,q,qbar);
input j,k,clk,rst;
output reg q;
output qbar;
always@(posedge clk or negedge rst)
begin
if (!rst) q <= 1'b0;
else begin
case({j,k})
2'b00 : q<=q;
2'b01 : q<=1'b0;
2'b10 : q<=1'b1;
2'b11 : q<=~q;
endcase
end
end
assign qbar = ~q;
endmodule
TestBench Code :
module tbmod_sixcounter;
reg clk,rst;
wire[2:0] q,qbar;
mod_six_counter DUT(.clk(clk),.rst(rst),.q(q),.qbar(qbar));
always #10 clk=~clk;
initial
begin
clk<=0;
rst<=0;
#7 rst<=1;

end
endmodule
-- *-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*
*
*
National
Engineering College, Kovilpatti ||
Autonomous
Institution || Affiliated to Anna University, Chennai
Accredited
by NAAC rCyArCO Grade & NBA* ||
NIRF 2022 RANK 169 || ARIIA
2021
RANK Band 'Excellent' 10th Rank (All India Level) || AICTE
- IIC 4 STAR
RATING
UG
|| B.E. - MECH*, -aECE*, CSE*, EEE*,
CIVIL || B.Tech.
- IT*,
Artificial
Intelligence and Data Science
PG
|| M.E. - Computer Science
& Engineering, Energy Engineering, High Voltage
Engineering, Embedded
Systems Technologies || M.Tech. rCo Information
Technology (Information and
Cyber Warfare)
39
Years of Academic Excellence ||
DST-FIST Sponsored
Institution || K.R.Innovation Centre ||
NewGen IEDC, DST, New Delhi
https://nec.edu.in <https://nec.edu.in>
|| Phone: 04632-222 502, 93859
76674, 93859 76684 || TNEA COUNSELLING CODE: 4962
**
--- Synchronet 3.21d-Linux NewsLink 1.2