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  • Concurrent assignment to a non-net q is not permitted

    From Indrayudh Nandy@indrayudh52@gmail.com to comp.lang.vhdl on Fri Jun 9 03:44:16 2023
    From Newsgroup: comp.lang.vhdl

    Hi,
    I am facing this error in vivado while writing a code for conversion of D flip flop to JK flip flop.
    Here is my code :
    module D_to_jk(j,k,clk,rst,q);
    input j,k,clk,rst;
    output reg q;
    wire w1,w2,w3,w4;
    wire q_bar;
    assign w1=~k;
    assign q_bar= ~q;
    assign w2= j&q_bar;
    assign w3= w1&q;
    assign w4= w2|w3;
    D d(w4,clk,rst,q);
    endmodule

    Please point me out the error so that I may rectify.
    Thanks
    Indrayudh
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  • From Richard Damon@Richard@Damon-Family.org to comp.lang.vhdl on Fri Jun 9 11:07:46 2023
    From Newsgroup: comp.lang.vhdl

    On 6/9/23 6:44 AM, Indrayudh Nandy wrote:
    Hi,
    I am facing this error in vivado while writing a code for conversion of D flip flop to JK flip flop.
    Here is my code :
    module D_to_jk(j,k,clk,rst,q);
    input j,k,clk,rst;
    output reg q;
    wire w1,w2,w3,w4;
    wire q_bar;
    assign w1=~k;
    assign q_bar= ~q;
    assign w2= j&q_bar;
    assign w3= w1&q;
    assign w4= w2|w3;
    D d(w4,clk,rst,q);
    endmodule

    Please point me out the error so that I may rectify.
    Thanks
    Indrayudh

    YOUR q needs to be a wire which you are connecting to the actual reg
    which will be in the D primative.
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  • From gnuarm.del...@gmail.com@gnuarm.deletethisbit@gmail.com to comp.lang.vhdl on Fri Jun 9 16:32:44 2023
    From Newsgroup: comp.lang.vhdl

    On Friday, June 9, 2023 at 6:44:18rC>AM UTC-4, Indrayudh Nandy wrote:
    Hi,
    I am facing this error in vivado while writing a code for conversion of D flip flop to JK flip flop.
    Here is my code :
    module D_to_jk(j,k,clk,rst,q);
    input j,k,clk,rst;
    output reg q;
    wire w1,w2,w3,w4;
    wire q_bar;
    assign w1=~k;
    assign q_bar= ~q;
    assign w2= j&q_bar;
    assign w3= w1&q;
    assign w4= w2|w3;
    D d(w4,clk,rst,q);
    endmodule

    Please point me out the error so that I may rectify.
    Thanks
    Indrayudh
    I think your biggest error, is trying to compile a Verilog program with a VHDL tool, perhaps?
    --
    Rick C.
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