From Newsgroup: comp.arch

scott@slp53.sl.home (Scott Lurndal) writes:

When I started at Burroughs, they had just started a project
to increase amount of memory that could be accessed by
an application on the medium systems (B3500) line. The
B3500 had a flat one million digit address space and
could run in rCycontrol staterCO or rCynormal staterCO. When the
base register had the value zero, the processor ran in
control state and privileged instructions were available,
otherwise the processor was is normal state and the
1md address space started at the privileged base register and
ended at the privileged limit register.

ThatrCOs an interesting approach! I had no idea how the Medium Systems
line worked.

YourCOd think yourCOd see a lot of experimentation around things like this nowadays that you can get your own open-source chip design fabbed
through Tiny Tapeout for US$300, including in IHPrCOs 350GHz 130nm SiGe
BiCMOS process. (Not 350MHz; fT is 350GHz.)

Without Tiny Tapeout, IHPrCOs MPW price for that rCLSG13G2rCY process is re47300/mm-# with a minimum of 0.8mm-#, which I find a rather daunting
pricetag for something that probably wonrCOt work the first time. As I understand it, that kind of thing is what sunk Chuck MoorerCOs chip design efforts at iTV in the 90s: they didnrCOt have enough capital to iterate
fast enough with MPW runs through MOSIS to ever ship a working chip.

New approaches to protection seem like an especially promising area as
we smash headfirst into the rCLvulnpocalypserCY and AI generates exploits
for the swiss-cheese computer systems the whole internet is built on.

Kragen
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From Newsgroup: comp.arch

On 9/11/26 04:13, Kragen Javier Sitaker wrote:

scott@slp53.sl.home (Scott Lurndal) writes:

When I started at Burroughs, they had just started a project
to increase amount of memory that could be accessed by
an application on the medium systems (B3500) line. The
B3500 had a flat one million digit address space and
could run in rCycontrol staterCO or rCynormal staterCO. When the
base register had the value zero, the processor ran in
control state and privileged instructions were available,
otherwise the processor was is normal state and the
1md address space started at the privileged base register and
ended at the privileged limit register.

ThatrCOs an interesting approach! I had no idea how the Medium Systems
line worked.

This is not an unusual approach. Many systems of the time used the same,
I know of the GE 400 line, and I believe the CDC 6x00.>
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From Newsgroup: comp.arch

On Fri, 11 Sep 2026 08:13:05 -0300, Kragen Javier Sitaker <kragen@canonical.org> wrote:

scott@slp53.sl.home (Scott Lurndal) writes:

When I started at Burroughs, they had just started a project
to increase amount of memory that could be accessed by
an application on the medium systems (B3500) line. The
B3500 had a flat one million digit address space and
could run in acontrol stateA or anormal stateA. When the
base register had the value zero, the processor ran in
control state and privileged instructions were available,
otherwise the processor was is normal state and the
1md address space started at the privileged base register and
ended at the privileged limit register.

ThatAs an interesting approach! I had no idea how the Medium Systems
line worked.

YouAd think youAd see a lot of experimentation around things like this >nowadays that you can get your own open-source chip design fabbed
through Tiny Tapeout for US$300, including in IHPAs 350GHz 130nm SiGe
BiCMOS process. (Not 350MHz; fT is 350GHz.)

Without Tiny Tapeout, IHPAs MPW price for that oSG13G2o process is
C7300/mm# with a minimum of 0.8mm#, which I find a rather daunting
pricetag for something that probably wonAt work the first time. As I >understand it, that kind of thing is what sunk Chuck MooreAs chip design >efforts at iTV in the 90s: they didnAt have enough capital to iterate
fast enough with MPW runs through MOSIS to ever ship a working chip.

New approaches to protection seem like an especially promising area as
we smash headfirst into the ovulnpocalypseo and AI generates exploits
for the swiss-cheese computer systems the whole internet is built on.

Kragen

I was talking to a college student yesterday who turns out to be an
opamp freak. We were arguing about what's our favorite gumdrop
higher-voltage opamp. I like OPA197 and he likes some OPA2xxx and
beats me on slew rate. Punk kid.

He has designed an IC CMOS opamp and is having some fabbed. Even kids
can do that nowadays.


John Larkin
Highland Tech Glen Canyon Design Center
Lunatic Fringe Electronics
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From Newsgroup: comp.arch

On 9/11/26 9:55 AM, john larkin wrote:

He has designed an IC CMOS opamp and is having some fabbed. Even kids
can do that nowadays.

They could do it in the 90's. You couldn't fit a lot onto a MOSIS
Tinychip in 2 micron but you could get stuff done. Without paying for it yourself as the professor usually had a budget for that sort of thing.
--
https://davesrocketworks.com
David Schultz
"It's just this little chromium switch here..."
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From Newsgroup: comp.arch

A one million bit address space means 2^20 or 20 bits. Partitioning memory into blocks has been around since the days of magnetic core memory. All those old machines used base registers, offset, registers, index registers or some other means to form addresses. It certainly simplified the opcode designation and address formation for memory access. Looks like it later eveloved into cache memory speedup which was premised on the assumption the code was working on data in reasonabe proximity in the memory. Magnetic core was slow, dynamic RAM was quick, and they were just getting used to the idea of static versus "volatile" memory.
--
For full context, visit https://www.electrondepot.com/electrodesign/segments-and-architectural-experimentation-was-re-segments-4410551-.htm

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