From Newsgroup: comp.arch

A fun thing I came across on Tue in my stacks of random papers, the Mascor 132 Reference Manual ca. 1970. It was a startup that failed in
the 1970 recession that a bunch of IBM ACS engineers went to before joining Amdahl. http://bitsavers.org/pdf/mascor I also added some
related historical articles to http://bitsavers.org/pdf/amdahl/history
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From Newsgroup: comp.arch


Al Kossow <aek@bitsavers.org> posted:

A fun thing I came across on Tue in my stacks of random papers, the Mascor 132 Reference Manual ca. 1970. It was a startup that failed in
the 1970 recession that a bunch of IBM ACS engineers went to before joining Amdahl. http://bitsavers.org/pdf/mascor I also added some
related historical articles to http://bitsavers.org/pdf/amdahl/history

I took a look over the ISA and it is not as bad as one could imagine
from taking a viewpoint embodied with computer knowledge from 1970.
I found several tid-bits similar to the evolutionarily path My 66000
has taken.

Quadiblock might learn a thing or two by giving it a study, too.
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From Newsgroup: comp.arch

MitchAlsup <user5857@newsgrouper.org.invalid> schrieb:

Al Kossow <aek@bitsavers.org> posted:

A fun thing I came across on Tue in my stacks of random papers, the Mascor 132 Reference Manual ca. 1970. It was a startup that failed in
the 1970 recession that a bunch of IBM ACS engineers went to before joining Amdahl. http://bitsavers.org/pdf/mascor I also added some
related historical articles to http://bitsavers.org/pdf/amdahl/history

I took a look over the ISA and it is not as bad as one could imagine
from taking a viewpoint embodied with computer knowledge from 1970.
I found several tid-bits similar to the evolutionarily path My 66000
has taken.

Going through the document now (not very deeply)

64 general purpose 32-bit registers, including for floating point
and integer. In the data in bitsavers, it is not desribed how
they handled 64-bit floating points (register pairs or otherwise).

Having either a base register or the IP for addressing sounds
familiar :-) They used segments as high bits of virtual
addresses, so only 16 MB effective address space.

Hexadecimal floats. Bah.

32-bit instructions, only four instrucion formats.

Six-bit constants instead of registers could be done.

If I read it correctly (sadly, the instruction listing is
missing from Bitsavers), the machine was similar to /360
in that one operand was destroyed.

Quadiblock might learn a thing or two by giving it a study, too.

+1
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From Newsgroup: comp.arch


Thomas Koenig <tkoenig@netcologne.de> posted:

MitchAlsup <user5857@newsgrouper.org.invalid> schrieb:

Al Kossow <aek@bitsavers.org> posted:

A fun thing I came across on Tue in my stacks of random papers, the Mascor 132 Reference Manual ca. 1970. It was a startup that failed in
the 1970 recession that a bunch of IBM ACS engineers went to before joining Amdahl. http://bitsavers.org/pdf/mascor I also added some
related historical articles to http://bitsavers.org/pdf/amdahl/history

I took a look over the ISA and it is not as bad as one could imagine
from taking a viewpoint embodied with computer knowledge from 1970.
I found several tid-bits similar to the evolutionarily path My 66000
has taken.

Going through the document now (not very deeply)

64 general purpose 32-bit registers, including for floating point
and integer. In the data in bitsavers, it is not desribed how
they handled 64-bit floating points (register pairs or otherwise).

one should assume pairing of registers.

Having either a base register or the IP for addressing sounds
familiar :-) They used segments as high bits of virtual
addresses, so only 16 MB effective address space.

Hexadecimal floats. Bah.

It was 1970...

32-bit instructions, only four instrucion formats.

Technically, IBM 360 only had 4 instruction formats...

Six-bit constants instead of registers could be done.

If I read it correctly (sadly, the instruction listing is
missing from Bitsavers), the machine was similar to /360
in that one operand was destroyed.

Not in the way ISA describes how instructions were performed,
and not in the control register model (sea of C registers.)

Quadiblock might learn a thing or two by giving it a study, too.

+1

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