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Calling conventions (particularly 32-bit ARM)

By David Brown on Mon Jan 6 14:57:51 2025

Latest reply by Waldek Hebisch on Tue Jan 7 02:11:45 2025
80286 protected mode (was: Byte ordering)

By Anton Ertl on Sun Jan 5 11:10:28 2025

Latest reply by Lynn Wheeler on Mon Jan 6 17:28:11 2025
Re: the 286, Byte ordering

By John Levine on Sun Jan 5 02:56:08 2025

Latest reply by Michael S on Mon Jan 6 15:19:32 2025
Re: 80286 protected mode

By David Brown on Fri Oct 11 14:10:13 2024

Latest reply by George Neuner on Sun Jan 5 23:01:29 2025
Re: Byte ordering

By MitchAlsup1 on Fri Oct 4 23:06:21 2024

Latest reply by Scott Lurndal on Fri Jan 3 18:11:53 2025
Re: Origins Of Interrupts

By Terje Mathisen on Sat Jan 4 17:36:30 2025

Latest reply by MitchAlsup1 on Fri Jan 3 23:03:28 2025
Re: Microarchitectural support for counting

By EricP on Fri Oct 4 14:11:23 2024

Latest reply by Scott Lurndal on Fri Jan 3 17:24:33 2025
What is an N-bit machine?

By John Dallman on Thu Nov 28 15:31:00 2024

Latest reply by Thomas Koenig on Thu Jan 2 09:59:32 2025
Re: Keeping other stuff with addresses

By David Schultz on Sun Dec 1 08:15:34 2024

Latest reply by Tim Rentsch on Tue Dec 31 08:46:28 2024
Re: Interview with Power's chief designer

By MitchAlsup1 on Sun Dec 29 01:58:52 2024

Latest reply by Thomas Koenig on Fri Dec 27 13:29:22 2024
Dealing with mispredictions (was: Microarchitectural support ...)

By Anton Ertl on Thu Dec 26 09:46:21 2024

Latest reply by Thomas Koenig on Thu Dec 26 22:27:51 2024
Re: bits and bytes, Keeping other stuff with addresses

By John Levine on Wed Dec 4 03:39:07 2024

Latest reply by MitchAlsup1 on Thu Dec 26 21:59:05 2024
What do we call non-pipelined designs?

By Marcus on Sun Dec 8 23:10:15 2024

Latest reply by EricP on Thu Dec 26 16:27:00 2024
Re: Strange asm generated by GCC...

By jseigh on Fri Dec 20 06:55:50 2024

Latest reply by jseigh on Tue Dec 24 08:26:05 2024
Where did CKD disks come from?

By John Levine on Thu Dec 12 20:31:53 2024

Latest reply by Lars Poulsen on Mon Dec 23 21:48:11 2024
Re: Memory ordering

By Tim Rentsch on Sat Nov 16 17:28:21 2024

Latest reply by EricP on Fri Dec 20 14:39:03 2024
Got Quake 2 running on my MRISC32 FPGA computer

By Marcus on Mon Dec 16 00:32:31 2024

Latest reply by Terje Mathisen on Mon Dec 16 15:32:26 2024
Re: portable proxy collector test...

By Brett on Fri Dec 6 19:55:07 2024

Latest reply by jseigh on Mon Dec 9 07:28:38 2024
IBM and Amdahl history (Re: What is an N-bit machine?)

By Anton Ertl on Fri Nov 29 07:22:28 2024

Latest reply by Lawrence D'Oliveiro on Sat Nov 30 23:21:28 2024
Re: Arm ldaxr / stxr loop question

By Scott Lurndal on Sat Nov 9 14:23:47 2024

Latest reply by Scott Lurndal on Fri Nov 22 15:45:20 2024
Re: In-Memory Computing

By MitchAlsup1 on Sun Nov 17 21:32:29 2024

Latest reply by Lawrence D'Oliveiro on Fri Nov 15 03:19:55 2024
Re: Brilliance

By Thomas Koenig on Sat Nov 16 22:28:12 2024

Latest reply by Terje Mathisen on Thu Nov 14 10:36:11 2024
Re: Memory ordering (was: Arm ldaxr / stxr loop question)

By Lawrence D'Oliveiro on Sat Nov 16 21:59:01 2024

Latest reply by Anton Ertl on Sat Nov 16 08:58:40 2024
Interpreters and indirect-branch prediction

By Anton Ertl on Wed Nov 13 08:20:27 2024

Latest reply by Anton Ertl on Thu Nov 14 08:35:41 2024
Re: Reverse engineering of Intel branch predictors

By Waldek Hebisch on Sun Nov 10 02:05:03 2024

Latest reply by MitchAlsup1 on Fri Nov 8 18:48:47 2024
Brilliance (was: Arm ldaxr / stxr loop question)

By Anton Ertl on Wed Nov 13 10:20:12 2024

Latest reply by Anton Ertl on Wed Nov 13 10:20:12 2024
Re: Semi OT Grace Hopper lecture

By Terje Mathisen on Sat Nov 9 22:39:46 2024

Latest reply by MitchAlsup1 on Fri Nov 8 21:37:24 2024
Re: Microsoft makes a lot of money, Is Intel exceptionally unsuccessful

By David Brown on Fri Sep 20 14:02:06 2024

Latest reply by Scott Lurndal on Mon Nov 4 15:51:52 2024
Re: Page fetching cache controller

By MitchAlsup1 on Thu Oct 31 19:11:47 2024

Latest reply by MitchAlsup1 on Thu Oct 31 19:11:47 2024
Re: old phones, x86S Specification

By John Levine on Fri Oct 25 16:53:41 2024

Latest reply by John Levine on Fri Oct 25 20:55:54 2024
Re: fine points of dynamic memory allocation, not 80286 protected mode

By Tim Rentsch on Fri Oct 18 07:12:51 2024

Latest reply by Tim Rentsch on Fri Oct 18 07:12:51 2024
Re: what's a mainframe, was is Vax addressing sane today

By Lynn Wheeler on Fri Sep 13 09:54:45 2024

Latest reply by Anton Ertl on Sat Oct 12 09:18:23 2024
Is Intel exceptionally unsuccessful as an architecture designer?

By John Dallman on Fri Sep 13 20:51:00 2024

Latest reply by Anton Ertl on Sat Oct 12 08:27:37 2024
Re: core memory, Historical evolution of CPU perf

By John Levine on Fri Oct 11 19:40:11 2024

Latest reply by Stephen Fuld on Fri Oct 11 16:36:18 2024
Re: Historical evolution of CPU perf

By Scott Lurndal on Fri Oct 11 14:40:59 2024

Latest reply by Thomas Koenig on Fri Oct 11 16:03:45 2024
Re: Byte ordering (was: Whether something is RISC or not)

By Anton Ertl on Fri Oct 4 17:30:07 2024

Latest reply by Lawrence D'Oliveiro on Sat Oct 5 06:31:02 2024
Re: Misc: BGBCC targeting RV64G, initial results...

By MitchAlsup1 on Fri Sep 27 15:52:34 2024

Latest reply by MitchAlsup1 on Sat Sep 28 00:43:49 2024
Re: Computer architects leaving Intel...

By Stephen Fuld on Fri Sep 13 13:09:00 2024

Latest reply by MitchAlsup1 on Fri Sep 27 18:01:40 2024
Local (predictive?) echoing (was: Is Intel exceptionally unsuccessful a

By Stefan Monnier on Fri Sep 20 10:57:12 2024

Latest reply by Stefan Monnier on Fri Sep 20 10:57:12 2024
Re: Address bits again, Article on new mainframe use

By MitchAlsup1 on Fri Sep 13 23:20:27 2024

Latest reply by Lawrence D'Oliveiro on Sat Sep 14 01:43:07 2024