From Newsgroup: comp.arch

According to Paul Clayton <paaronclayton@gmail.com>:

I do not know if being able to have an interrupt in the middle of an >assembly instruction is a violation of the assembly contract. (In
theory, a few special cases might be handled such that the assembly >instruction that breaks into more than one machine instruction is
handled similarly to breaking instructions into -|ops.) ...

That horse left the barn a long, long time ago.

IN 1963 the PDP-6 had a block transfer instruction that took the source and destination addresses from the left and right halves of a register and the end of the destination as the instruction's operand. If there was an interrupt, it updated the register so the transfer could resume when the interrupt returned. The PDP-10 series all did the same thing, and as someone else noted there were similar instructions on the Vax. The possibility of the register changing was part of the assembly contract, so you'd be sorry if you used that register as the index register for the operand address, ruling out an otherwise clever technique for encoding the length of the move.

The S/370 MOVE LONG instruction does the same thing. Any system with paged virtual memory and a block move instruction has to do that or it's going to have
trouble dealing with page faults in the middle of a move. (I suppose it could check that all the pages were resident before starting the move and fault then, but now you have an instruction that can cause thrashing or worse.)

This doesn't have to be a big deal. It mostly means that the architecture says that if an instruction is interruptible, the contents of some of the registers it uses are unpredictable.
--
Regards,
John Levine, johnl@taugh.com, Primary Perpetrator of "The Internet for Dummies",
Please consider the environment before reading this e-mail. https://jl.ly
--- Synchronet 3.21b-Linux NewsLink 1.2

From Newsgroup: comp.arch

On 1/27/2026 8:47 PM, John Levine wrote:

According to Paul Clayton <paaronclayton@gmail.com>:

I do not know if being able to have an interrupt in the middle of an
assembly instruction is a violation of the assembly contract. (In
theory, a few special cases might be handled such that the assembly
instruction that breaks into more than one machine instruction is
handled similarly to breaking instructions into -|ops.) ...

That horse left the barn a long, long time ago.

IN 1963 the PDP-6 had a block transfer instruction that took the source and destination addresses from the left and right halves of a register and the end
of the destination as the instruction's operand. If there was an interrupt, it
updated the register so the transfer could resume when the interrupt returned.
The PDP-10 series all did the same thing, and as someone else noted there were
similar instructions on the Vax. The possibility of the register changing was part of the assembly contract, so you'd be sorry if you used that register as the index register for the operand address, ruling out an otherwise clever technique for encoding the length of the move.

Even slightly earlier than that. In 1962, the Univac 1107 had a similar
block transfer instruction (slightly different location of operands) and
also had "search" instructions that could search multiple memory
locations for a value that was equal, not equal, greater than, less than
or equal to or within or not within a range of values specified in a
register. All were interruptible as you described above.
--
- Stephen Fuld
(e-mail address disguised to prevent spam)
--- Synchronet 3.21b-Linux NewsLink 1.2