| Sysop: | Amessyroom |
|---|---|
| Location: | Fayetteville, NC |
| Users: | 23 |
| Nodes: | 6 (0 / 6) |
| Uptime: | 54:32:52 |
| Calls: | 583 |
| Files: | 1,139 |
| D/L today: |
179 files (27,921K bytes) |
| Messages: | 111,800 |
On 12/08/2025 1:50 am, john larkin wrote:
On Mon, 11 Aug 2025 07:27:37 -0700, Don Y
<blockedofcourse@foo.invalid> wrote:
On 8/11/2025 5:12 AM, BillGill wrote:
On 8/10/2025 9:27 AM, Don Y wrote:
<snip>
We design hardware that way. We seldom know or care about the
internals of components. We design from data sheets or experiments and
simulate using ideal components and encrypted behavioral models.
Since the inductors in your Spice simulations rarely have the data sheet >parallel capacitance plugged into the Spice model of your inductor, you >clearly don't care as much as you should about the internals of at least >some of your components.
On Tue, 12 Aug 2025 03:32:16 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 12/08/2025 1:50 am, john larkin wrote:
On Mon, 11 Aug 2025 07:27:37 -0700, Don Y
<blockedofcourse@foo.invalid> wrote:
On 8/11/2025 5:12 AM, BillGill wrote:
On 8/10/2025 9:27 AM, Don Y wrote:
<snip>
We design hardware that way. We seldom know or care about the
internals of components. We design from data sheets or experiments and
simulate using ideal components and encrypted behavioral models.
Since the inductors in your Spice simulations rarely have the data sheet
parallel capacitance plugged into the Spice model of your inductor, you
clearly don't care as much as you should about the internals of at least
some of your components.
I care when it matters. Inductor SRF rarely does.
festooning a sim with a bunch of useless parts slows it down, if it doesn't flat break
it.
I have one thing I'm running sims on now, a sort-of-gyrated
complex-impedance dummy load, that runs long enough for snacks and
naps.
I design stuff and people keep buying it. How are your latest designs selling?
On 12/08/2025 9:19 am, john larkin wrote:
On Tue, 12 Aug 2025 03:32:16 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 12/08/2025 1:50 am, john larkin wrote:
On Mon, 11 Aug 2025 07:27:37 -0700, Don Y
<blockedofcourse@foo.invalid> wrote:
On 8/11/2025 5:12 AM, BillGill wrote:
On 8/10/2025 9:27 AM, Don Y wrote:
<snip>
We design hardware that way. We seldom know or care about the
internals of components. We design from data sheets or experiments and >>>> simulate using ideal components and encrypted behavioral models.
Since the inductors in your Spice simulations rarely have the data sheet >>> parallel capacitance plugged into the Spice model of your inductor, you
clearly don't care as much as you should about the internals of at least >>> some of your components.
I care when it matters. Inductor SRF rarely does.
If you only design very slow stuff, that may be true.
festooning a sim with a bunch of useless parts slows it down, if it doesn't flat break
it.
If the parts are useful in the real world circuit, it pays to leave them
in the sim. Something that simulates wonderfully, but oscillates in the
real world isn't all that useful.
I have one thing I'm running sims on now, a sort-of-gyrated
complex-impedance dummy load, that runs long enough for snacks and
naps.
That usually means that there some parasitic high frequency oscillator
in there, constraining the maximun step ti\me to something
inconveniently low.
I design stuff and people keep buying it. How are your latest designs
selling?
You've set up a vanity electronic design service that sells bespoke >electronic design to people too lazy or dim to work out how to use
off-the shelf hardware. It's a business model of which I'm deeply
envious, but I've got this inconvenient compulsion to be truthful,
puts it out of my reach. My most recent design work was for Haffmans
B,V. in Venlo, in 2000-2003, and it's probably still selling into the >brewing industry.
If one of their competitors had the wit to set up a four terminal liquid >conductivity meter - as I wanted to do, but the boss wasn't prepared to
pay for a new (very small) printed circuit board - they might have eaten >what market there was.
On Tue, 12 Aug 2025 16:19:25 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 12/08/2025 9:19 am, john larkin wrote:
On Tue, 12 Aug 2025 03:32:16 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 12/08/2025 1:50 am, john larkin wrote:
On Mon, 11 Aug 2025 07:27:37 -0700, Don Y
<blockedofcourse@foo.invalid> wrote:
On 8/11/2025 5:12 AM, BillGill wrote:
On 8/10/2025 9:27 AM, Don Y wrote:
I design stuff and people keep buying it. How are your latest designs
selling?
You've set up a vanity electronic design service that sells bespoke
electronic design to people too lazy or dim to work out how to use
off-the shelf hardware. It's a business model of which I'm deeply
envious, but I've got this inconvenient compulsion to be truthful,
No. Your compulsion is to be nasty and insulting because you are
insecure and have no imagination.
which
puts it out of my reach. My most recent design work was for Haffmans
B,V. in Venlo, in 2000-2003, and it's probably still selling into the
brewing industry.
If one of their competitors had the wit to set up a four terminal liquid
conductivity meter - as I wanted to do, but the boss wasn't prepared to
pay for a new (very small) printed circuit board - they might have eaten
what market there was.
An insulated toroidal inductor would be a great liquid conductivity
sensor.
On Tue, 12 Aug 2025 16:19:25 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 12/08/2025 9:19 am, john larkin wrote:
On Tue, 12 Aug 2025 03:32:16 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 12/08/2025 1:50 am, john larkin wrote:
On Mon, 11 Aug 2025 07:27:37 -0700, Don Y
<blockedofcourse@foo.invalid> wrote:
On 8/11/2025 5:12 AM, BillGill wrote:
On 8/10/2025 9:27 AM, Don Y wrote:
<snip>
We design hardware that way. We seldom know or care about the
internals of components. We design from data sheets or experiments and >>>>> simulate using ideal components and encrypted behavioral models.
Since the inductors in your Spice simulations rarely have the data sheet >>>> parallel capacitance plugged into the Spice model of your inductor, you >>>> clearly don't care as much as you should about the internals of at least >>>> some of your components.
I care when it matters. Inductor SRF rarely does.
If you only design very slow stuff, that may be true.
20 GHz wideband e/o modulators with picosecond resolution timing
generators is about our limit. We're getting lazy, I guess.
On 13/08/2025 12:37 am, john larkin wrote:
On Tue, 12 Aug 2025 16:19:25 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 12/08/2025 9:19 am, john larkin wrote:
On Tue, 12 Aug 2025 03:32:16 +1000, Bill Sloman <bill.sloman@ieee.org> >>>> wrote:
On 12/08/2025 1:50 am, john larkin wrote:
On Mon, 11 Aug 2025 07:27:37 -0700, Don Y
<blockedofcourse@foo.invalid> wrote:
On 8/11/2025 5:12 AM, BillGill wrote:
On 8/10/2025 9:27 AM, Don Y wrote:
<snip>
We design hardware that way. We seldom know or care about the
internals of components. We design from data sheets or experiments and >>>>>> simulate using ideal components and encrypted behavioral models.
Since the inductors in your Spice simulations rarely have the data sheet >>>>> parallel capacitance plugged into the Spice model of your inductor, you >>>>> clearly don't care as much as you should about the internals of at least >>>>> some of your components.
I care when it matters. Inductor SRF rarely does.
If you only design very slow stuff, that may be true.
20 GHz wideband e/o modulators with picosecond resolution timing
generators is about our limit. We're getting lazy, I guess.
Scarcely a circuit which would use use much in the way of wound
inductors - they might show up in the power supplies, but at 20GHz >everything starts looking like a transmission line where the parallel >capacitance is an integral part of the circuit. That was certainly true
for the 1 GHz stuff that I did forty years ago.
I am aware that you do "design" fast stuff, though design doesn't seem
to be quite the right word for your approach.
On Sun, 17 Aug 2025 02:17:33 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 13/08/2025 12:37 am, john larkin wrote:
On Tue, 12 Aug 2025 16:19:25 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 12/08/2025 9:19 am, john larkin wrote:
On Tue, 12 Aug 2025 03:32:16 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>> wrote:
On 12/08/2025 1:50 am, john larkin wrote:
On Mon, 11 Aug 2025 07:27:37 -0700, Don Y
<blockedofcourse@foo.invalid> wrote:
On 8/11/2025 5:12 AM, BillGill wrote:
On 8/10/2025 9:27 AM, Don Y wrote:
<snip>
We design hardware that way. We seldom know or care about the
internals of components. We design from data sheets or experiments and >>>>>>> simulate using ideal components and encrypted behavioral models.
Since the inductors in your Spice simulations rarely have the data sheet >>>>>> parallel capacitance plugged into the Spice model of your inductor, you >>>>>> clearly don't care as much as you should about the internals of at least >>>>>> some of your components.
I care when it matters. Inductor SRF rarely does.
If you only design very slow stuff, that may be true.
20 GHz wideband e/o modulators with picosecond resolution timing
generators is about our limit. We're getting lazy, I guess.
Scarcely a circuit which would use use much in the way of wound
inductors - they might show up in the power supplies, but at 20GHz
everything starts looking like a transmission line where the parallel
capacitance is an integral part of the circuit. That was certainly true
for the 1 GHz stuff that I did forty years ago.
Distributed amplifier bias networks tend to use inductors. Some people
like those dreadful conical things, but there are better ways.
Lots of people make conicals now that the Piconics patents have timed
out.
I am aware that you do "design" fast stuff, though design doesn't seem
to be quite the right word for your approach.
I accept that we have different approaches to electronic design. My
approach is to actually build stuff that works and sells.
On 17/08/2025 6:40 am, john larkin wrote:
On Sun, 17 Aug 2025 02:17:33 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 13/08/2025 12:37 am, john larkin wrote:
On Tue, 12 Aug 2025 16:19:25 +1000, Bill Sloman <bill.sloman@ieee.org> >>>> wrote:
On 12/08/2025 9:19 am, john larkin wrote:
On Tue, 12 Aug 2025 03:32:16 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>> wrote:
On 12/08/2025 1:50 am, john larkin wrote:
On Mon, 11 Aug 2025 07:27:37 -0700, Don Y
<blockedofcourse@foo.invalid> wrote:
On 8/11/2025 5:12 AM, BillGill wrote:
On 8/10/2025 9:27 AM, Don Y wrote:
<snip>
We design hardware that way. We seldom know or care about theSince the inductors in your Spice simulations rarely have the data sheet
internals of components. We design from data sheets or experiments and >>>>>>>> simulate using ideal components and encrypted behavioral models. >>>>>>>
parallel capacitance plugged into the Spice model of your inductor, you >>>>>>> clearly don't care as much as you should about the internals of at least
some of your components.
I care when it matters. Inductor SRF rarely does.
If you only design very slow stuff, that may be true.
20 GHz wideband e/o modulators with picosecond resolution timing
generators is about our limit. We're getting lazy, I guess.
Scarcely a circuit which would use use much in the way of wound
inductors - they might show up in the power supplies, but at 20GHz
everything starts looking like a transmission line where the parallel
capacitance is an integral part of the circuit. That was certainly true
for the 1 GHz stuff that I did forty years ago.
Distributed amplifier bias networks tend to use inductors. Some people
like those dreadful conical things, but there are better ways.
Lots of people make conicals now that the Piconics patents have timed
out.
I am aware that you do "design" fast stuff, though design doesn't seem
to be quite the right word for your approach.
I accept that we have different approaches to electronic design. My
approach is to actually build stuff that works and sells.
So was mine, back when I could find people to hire me. The 1GHz stuff
ended up in a product Cambridge Instruments sold. I even got a patent
out of it.
"U.K. patent 2139411 "Moving Plate" (also US patent 4614872) on an
improved blanking system for charged particle beams, easily adjusted to >match a wide range of particle velocities; assigned to Cambridge
Instruments in 1983."
The boss wanted our voltage contrast electron microscope to be also
capable of EBIC (electron beam-induced current), so the beam-blanking
system had to cope with beam voltages from 15kV to 300V - blanking
plates long enough (18mm) to bend a 15kV had more than 0.5nsec transit
time for a 300V beam. If you could set the electrodes parallel to the
beam for the 15KV beam, and rotate them until they were at right angle
to beam for beam voltages less than about 800V you could shorten up the >region of interaction enough to stay out of trouble.
We did push the envelope a bit further than you seem to.
On Sun, 17 Aug 2025 14:35:04 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 17/08/2025 6:40 am, john larkin wrote:
On Sun, 17 Aug 2025 02:17:33 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 13/08/2025 12:37 am, john larkin wrote:
On Tue, 12 Aug 2025 16:19:25 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>> wrote:
On 12/08/2025 9:19 am, john larkin wrote:
On Tue, 12 Aug 2025 03:32:16 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>>> wrote:
On 12/08/2025 1:50 am, john larkin wrote:
On Mon, 11 Aug 2025 07:27:37 -0700, Don Y
<blockedofcourse@foo.invalid> wrote:
On 8/11/2025 5:12 AM, BillGill wrote:
On 8/10/2025 9:27 AM, Don Y wrote:
<snip>
We design hardware that way. We seldom know or care about the >>>>>>>>> internals of components. We design from data sheets or experiments andSince the inductors in your Spice simulations rarely have the data sheet
simulate using ideal components and encrypted behavioral models. >>>>>>>>
parallel capacitance plugged into the Spice model of your inductor, you
clearly don't care as much as you should about the internals of at least
some of your components.
I care when it matters. Inductor SRF rarely does.
If you only design very slow stuff, that may be true.
20 GHz wideband e/o modulators with picosecond resolution timing
generators is about our limit. We're getting lazy, I guess.
Scarcely a circuit which would use use much in the way of wound
inductors - they might show up in the power supplies, but at 20GHz
everything starts looking like a transmission line where the parallel
capacitance is an integral part of the circuit. That was certainly true >>>> for the 1 GHz stuff that I did forty years ago.
Distributed amplifier bias networks tend to use inductors. Some people
like those dreadful conical things, but there are better ways.
Lots of people make conicals now that the Piconics patents have timed
out.
I am aware that you do "design" fast stuff, though design doesn't seem >>>> to be quite the right word for your approach.
I accept that we have different approaches to electronic design. My
approach is to actually build stuff that works and sells.
So was mine, back when I could find people to hire me. The 1GHz stuff
ended up in a product Cambridge Instruments sold. I even got a patent
out of it.
"U.K. patent 2139411 "Moving Plate" (also US patent 4614872) on an
improved blanking system for charged particle beams, easily adjusted to
match a wide range of particle velocities; assigned to Cambridge
Instruments in 1983."
The boss wanted our voltage contrast electron microscope to be also
capable of EBIC (electron beam-induced current), so the beam-blanking
system had to cope with beam voltages from 15kV to 300V - blanking
plates long enough (18mm) to bend a 15kV had more than 0.5nsec transit
time for a 300V beam. If you could set the electrodes parallel to the
beam for the 15KV beam, and rotate them until they were at right angle
to beam for beam voltages less than about 800V you could shorten up the
region of interaction enough to stay out of trouble.
We did push the envelope a bit further than you seem to.
We did the picosecond master timing system and multi-GHz beam
modulators for the world's biggest laser. That was fun. The Livermore
people are wonderful to work with. We always seemed to work with a
genius female physicist who did the heavy thinking.
https://www.llnl.gov/article/48771/nif-welcomes-100000th-visitor
We're not sure which of us was actually # 100,000.
On 18/08/2025 1:31 am, john larkin wrote:
On Sun, 17 Aug 2025 14:35:04 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 17/08/2025 6:40 am, john larkin wrote:
On Sun, 17 Aug 2025 02:17:33 +1000, Bill Sloman <bill.sloman@ieee.org> >>>> wrote:
On 13/08/2025 12:37 am, john larkin wrote:
On Tue, 12 Aug 2025 16:19:25 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>> wrote:
On 12/08/2025 9:19 am, john larkin wrote:
On Tue, 12 Aug 2025 03:32:16 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>>>> wrote:
On 12/08/2025 1:50 am, john larkin wrote:
On Mon, 11 Aug 2025 07:27:37 -0700, Don Y
<blockedofcourse@foo.invalid> wrote:
On 8/11/2025 5:12 AM, BillGill wrote:
On 8/10/2025 9:27 AM, Don Y wrote:
<snip>
We design hardware that way. We seldom know or care about the >>>>>>>>>> internals of components. We design from data sheets or experiments andSince the inductors in your Spice simulations rarely have the data sheet
simulate using ideal components and encrypted behavioral models. >>>>>>>>>
parallel capacitance plugged into the Spice model of your inductor, you
clearly don't care as much as you should about the internals of at least
some of your components.
I care when it matters. Inductor SRF rarely does.
If you only design very slow stuff, that may be true.
20 GHz wideband e/o modulators with picosecond resolution timing
generators is about our limit. We're getting lazy, I guess.
Scarcely a circuit which would use use much in the way of wound
inductors - they might show up in the power supplies, but at 20GHz
everything starts looking like a transmission line where the parallel >>>>> capacitance is an integral part of the circuit. That was certainly true >>>>> for the 1 GHz stuff that I did forty years ago.
Distributed amplifier bias networks tend to use inductors. Some people >>>> like those dreadful conical things, but there are better ways.
Lots of people make conicals now that the Piconics patents have timed
out.
I am aware that you do "design" fast stuff, though design doesn't seem >>>>> to be quite the right word for your approach.
I accept that we have different approaches to electronic design. My
approach is to actually build stuff that works and sells.
So was mine, back when I could find people to hire me. The 1GHz stuff
ended up in a product Cambridge Instruments sold. I even got a patent
out of it.
"U.K. patent 2139411 "Moving Plate" (also US patent 4614872) on an
improved blanking system for charged particle beams, easily adjusted to
match a wide range of particle velocities; assigned to Cambridge
Instruments in 1983."
The boss wanted our voltage contrast electron microscope to be also
capable of EBIC (electron beam-induced current), so the beam-blanking
system had to cope with beam voltages from 15kV to 300V - blanking
plates long enough (18mm) to bend a 15kV had more than 0.5nsec transit
time for a 300V beam. If you could set the electrodes parallel to the
beam for the 15KV beam, and rotate them until they were at right angle
to beam for beam voltages less than about 800V you could shorten up the
region of interaction enough to stay out of trouble.
We did push the envelope a bit further than you seem to.
We did the picosecond master timing system and multi-GHz beam
modulators for the world's biggest laser. That was fun. The Livermore
people are wonderful to work with. We always seemed to work with a
genius female physicist who did the heavy thinking.
Of course your scheme was taken from the Hewlett-Packard Journal, and
made a lot more sense back when it was invented.
Now that we've got really low jitter local oscillators - not as stable
as atomic clocks, but with quite a bit less jitter - a common clock does >make a lot more sense (even if it depends on a lump of sapphire immersed
in liquid helium and seems to have been invented in Western Australia
for the Australian over the horizon radar system).
One of the more depressing features of the Review of Scientific
Instruments is way it reveals that American physicists don't take >electronics all that seriously. The one time I dropped your name on a >physicists from the NIF he was wasn't in the least impressed.
https://www.llnl.gov/article/48771/nif-welcomes-100000th-visitor
We're not sure which of us was actually # 100,000.
And why would you care?
On Mon, 18 Aug 2025 02:47:24 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 18/08/2025 1:31 am, john larkin wrote:
On Sun, 17 Aug 2025 14:35:04 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 17/08/2025 6:40 am, john larkin wrote:
On Sun, 17 Aug 2025 02:17:33 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>> wrote:
On 13/08/2025 12:37 am, john larkin wrote:
On Tue, 12 Aug 2025 16:19:25 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>>> wrote:
On 12/08/2025 9:19 am, john larkin wrote:
On Tue, 12 Aug 2025 03:32:16 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 12/08/2025 1:50 am, john larkin wrote:
On Mon, 11 Aug 2025 07:27:37 -0700, Don Y
<blockedofcourse@foo.invalid> wrote:
On 8/11/2025 5:12 AM, BillGill wrote:
On 8/10/2025 9:27 AM, Don Y wrote:
<snip>
We design hardware that way. We seldom know or care about the >>>>>>>>>>> internals of components. We design from data sheets or experiments andSince the inductors in your Spice simulations rarely have the data sheet
simulate using ideal components and encrypted behavioral models. >>>>>>>>>>
parallel capacitance plugged into the Spice model of your inductor, you
clearly don't care as much as you should about the internals of at least
some of your components.
I care when it matters. Inductor SRF rarely does.
If you only design very slow stuff, that may be true.
20 GHz wideband e/o modulators with picosecond resolution timing >>>>>>> generators is about our limit. We're getting lazy, I guess.
Scarcely a circuit which would use use much in the way of wound
inductors - they might show up in the power supplies, but at 20GHz >>>>>> everything starts looking like a transmission line where the parallel >>>>>> capacitance is an integral part of the circuit. That was certainly true >>>>>> for the 1 GHz stuff that I did forty years ago.
Distributed amplifier bias networks tend to use inductors. Some people >>>>> like those dreadful conical things, but there are better ways.
Lots of people make conicals now that the Piconics patents have timed >>>>> out.
I am aware that you do "design" fast stuff, though design doesn't seem >>>>>> to be quite the right word for your approach.
I accept that we have different approaches to electronic design. My
approach is to actually build stuff that works and sells.
So was mine, back when I could find people to hire me. The 1GHz stuff
ended up in a product Cambridge Instruments sold. I even got a patent >>>> out of it.
"U.K. patent 2139411 "Moving Plate" (also US patent 4614872) on an
improved blanking system for charged particle beams, easily adjusted to >>>> match a wide range of particle velocities; assigned to Cambridge
Instruments in 1983."
The boss wanted our voltage contrast electron microscope to be also
capable of EBIC (electron beam-induced current), so the beam-blanking
system had to cope with beam voltages from 15kV to 300V - blanking
plates long enough (18mm) to bend a 15kV had more than 0.5nsec transit >>>> time for a 300V beam. If you could set the electrodes parallel to the
beam for the 15KV beam, and rotate them until they were at right angle >>>> to beam for beam voltages less than about 800V you could shorten up the >>>> region of interaction enough to stay out of trouble.
We did push the envelope a bit further than you seem to.
We did the picosecond master timing system and multi-GHz beam
modulators for the world's biggest laser. That was fun. The Livermore
people are wonderful to work with. We always seemed to work with a
genius female physicist who did the heavy thinking.
Of course your scheme was taken from the Hewlett-Packard Journal, and
made a lot more sense back when it was invented.
HP's vernier-locked digital delay generators and picosecond time
interval counters were big and clumsy, not worth copying. I'm not
aware that HP did any eo modulators.
Got references? Thought not.
On 18/08/2025 3:23 am, john larkin wrote:
On Mon, 18 Aug 2025 02:47:24 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 18/08/2025 1:31 am, john larkin wrote:
On Sun, 17 Aug 2025 14:35:04 +1000, Bill Sloman <bill.sloman@ieee.org> >>>> wrote:
On 17/08/2025 6:40 am, john larkin wrote:
On Sun, 17 Aug 2025 02:17:33 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>> wrote:
On 13/08/2025 12:37 am, john larkin wrote:
On Tue, 12 Aug 2025 16:19:25 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>>>> wrote:
On 12/08/2025 9:19 am, john larkin wrote:
On Tue, 12 Aug 2025 03:32:16 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 12/08/2025 1:50 am, john larkin wrote:
On Mon, 11 Aug 2025 07:27:37 -0700, Don Y
<blockedofcourse@foo.invalid> wrote:
On 8/11/2025 5:12 AM, BillGill wrote:
On 8/10/2025 9:27 AM, Don Y wrote:
<snip>
We design hardware that way. We seldom know or care about the >>>>>>>>>>>> internals of components. We design from data sheets or experiments andSince the inductors in your Spice simulations rarely have the data sheet
simulate using ideal components and encrypted behavioral models. >>>>>>>>>>>
parallel capacitance plugged into the Spice model of your inductor, you
clearly don't care as much as you should about the internals of at least
some of your components.
I care when it matters. Inductor SRF rarely does.
If you only design very slow stuff, that may be true.
20 GHz wideband e/o modulators with picosecond resolution timing >>>>>>>> generators is about our limit. We're getting lazy, I guess.
Scarcely a circuit which would use use much in the way of wound
inductors - they might show up in the power supplies, but at 20GHz >>>>>>> everything starts looking like a transmission line where the parallel >>>>>>> capacitance is an integral part of the circuit. That was certainly true >>>>>>> for the 1 GHz stuff that I did forty years ago.
Distributed amplifier bias networks tend to use inductors. Some people >>>>>> like those dreadful conical things, but there are better ways.
Lots of people make conicals now that the Piconics patents have timed >>>>>> out.
I am aware that you do "design" fast stuff, though design doesn't seem >>>>>>> to be quite the right word for your approach.
I accept that we have different approaches to electronic design. My >>>>>> approach is to actually build stuff that works and sells.
So was mine, back when I could find people to hire me. The 1GHz stuff >>>>> ended up in a product Cambridge Instruments sold. I even got a patent >>>>> out of it.
"U.K. patent 2139411 "Moving Plate" (also US patent 4614872) on an
improved blanking system for charged particle beams, easily adjusted to >>>>> match a wide range of particle velocities; assigned to Cambridge
Instruments in 1983."
The boss wanted our voltage contrast electron microscope to be also
capable of EBIC (electron beam-induced current), so the beam-blanking >>>>> system had to cope with beam voltages from 15kV to 300V - blanking
plates long enough (18mm) to bend a 15kV had more than 0.5nsec transit >>>>> time for a 300V beam. If you could set the electrodes parallel to the >>>>> beam for the 15KV beam, and rotate them until they were at right angle >>>>> to beam for beam voltages less than about 800V you could shorten up the >>>>> region of interaction enough to stay out of trouble.
We did push the envelope a bit further than you seem to.
We did the picosecond master timing system and multi-GHz beam
modulators for the world's biggest laser. That was fun. The Livermore
people are wonderful to work with. We always seemed to work with a
genius female physicist who did the heavy thinking.
Of course your scheme was taken from the Hewlett-Packard Journal, and
made a lot more sense back when it was invented.
HP's vernier-locked digital delay generators and picosecond time
interval counters were big and clumsy, not worth copying. I'm not
aware that HP did any eo modulators.
Got references? Thought not.
It was you who made the claim, here, years ago.
I presume "big and clumsy and not worth copying" means that you tried
and failed.
On Mon, 18 Aug 2025 21:08:56 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 18/08/2025 3:23 am, john larkin wrote:
On Mon, 18 Aug 2025 02:47:24 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 18/08/2025 1:31 am, john larkin wrote:
On Sun, 17 Aug 2025 14:35:04 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>> wrote:
On 17/08/2025 6:40 am, john larkin wrote:
On Sun, 17 Aug 2025 02:17:33 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>>> wrote:
On 13/08/2025 12:37 am, john larkin wrote:
On Tue, 12 Aug 2025 16:19:25 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 12/08/2025 9:19 am, john larkin wrote:
On Tue, 12 Aug 2025 03:32:16 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 12/08/2025 1:50 am, john larkin wrote:
On Mon, 11 Aug 2025 07:27:37 -0700, Don Y
<blockedofcourse@foo.invalid> wrote:
On 8/11/2025 5:12 AM, BillGill wrote:
On 8/10/2025 9:27 AM, Don Y wrote:
<snip>
We design hardware that way. We seldom know or care about the >>>>>>>>>>>>> internals of components. We design from data sheets or experiments andSince the inductors in your Spice simulations rarely have the data sheet
simulate using ideal components and encrypted behavioral models. >>>>>>>>>>>>
parallel capacitance plugged into the Spice model of your inductor, you
clearly don't care as much as you should about the internals of at least
some of your components.
I care when it matters. Inductor SRF rarely does.
If you only design very slow stuff, that may be true.
20 GHz wideband e/o modulators with picosecond resolution timing >>>>>>>>> generators is about our limit. We're getting lazy, I guess.
Scarcely a circuit which would use use much in the way of wound >>>>>>>> inductors - they might show up in the power supplies, but at 20GHz >>>>>>>> everything starts looking like a transmission line where the parallel >>>>>>>> capacitance is an integral part of the circuit. That was certainly true
for the 1 GHz stuff that I did forty years ago.
Distributed amplifier bias networks tend to use inductors. Some people >>>>>>> like those dreadful conical things, but there are better ways.
Lots of people make conicals now that the Piconics patents have timed >>>>>>> out.
I am aware that you do "design" fast stuff, though design doesn't seem >>>>>>>> to be quite the right word for your approach.
I accept that we have different approaches to electronic design. My >>>>>>> approach is to actually build stuff that works and sells.
So was mine, back when I could find people to hire me. The 1GHz stuff >>>>>> ended up in a product Cambridge Instruments sold. I even got a patent >>>>>> out of it.
"U.K. patent 2139411 "Moving Plate" (also US patent 4614872) on an >>>>>> improved blanking system for charged particle beams, easily adjusted to >>>>>> match a wide range of particle velocities; assigned to Cambridge
Instruments in 1983."
The boss wanted our voltage contrast electron microscope to be also >>>>>> capable of EBIC (electron beam-induced current), so the beam-blanking >>>>>> system had to cope with beam voltages from 15kV to 300V - blanking >>>>>> plates long enough (18mm) to bend a 15kV had more than 0.5nsec transit >>>>>> time for a 300V beam. If you could set the electrodes parallel to the >>>>>> beam for the 15KV beam, and rotate them until they were at right angle >>>>>> to beam for beam voltages less than about 800V you could shorten up the >>>>>> region of interaction enough to stay out of trouble.
We did push the envelope a bit further than you seem to.
We did the picosecond master timing system and multi-GHz beam
modulators for the world's biggest laser. That was fun. The Livermore >>>>> people are wonderful to work with. We always seemed to work with a
genius female physicist who did the heavy thinking.
Of course your scheme was taken from the Hewlett-Packard Journal, and
made a lot more sense back when it was invented.
HP's vernier-locked digital delay generators and picosecond time
interval counters were big and clumsy, not worth copying. I'm not
aware that HP did any eo modulators.
Got references? Thought not.
It was you who made the claim, here, years ago.
I presume "big and clumsy and not worth copying" means that you tried
and failed.
No. The 5370 time interval counter and their time synthesizer box used
a triggered delay-line oscillator and a frequency heterodyne phase
locker. That was complex and had huge insertion delays and lots of
jitter.
Their (Keysights's) latest time interval counter has lots of jitter
too.
This summarizes known (to me) DDG architectures:
https://en.wikipedia.org/wiki/Digital_delay_generator#Design
I wrote that part.
On Mon, 18 Aug 2025 07:10:24 -0700, john larkin <jl@glen--canyon.com>
wrote:
On Mon, 18 Aug 2025 21:08:56 +1000, Bill Sloman <bill.sloman@ieee.org> >>wrote:
On 18/08/2025 3:23 am, john larkin wrote:
On Mon, 18 Aug 2025 02:47:24 +1000, Bill Sloman <bill.sloman@ieee.org> >>>> wrote:
On 18/08/2025 1:31 am, john larkin wrote:
On Sun, 17 Aug 2025 14:35:04 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>> wrote:
On 17/08/2025 6:40 am, john larkin wrote:
On Sun, 17 Aug 2025 02:17:33 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>>>> wrote:
On 13/08/2025 12:37 am, john larkin wrote:
On Tue, 12 Aug 2025 16:19:25 +1000, Bill Sloman <bill.sloman@ieee.org>Scarcely a circuit which would use use much in the way of wound >>>>>>>>> inductors - they might show up in the power supplies, but at 20GHz >>>>>>>>> everything starts looking like a transmission line where the parallel >>>>>>>>> capacitance is an integral part of the circuit. That was certainly true
wrote:
On 12/08/2025 9:19 am, john larkin wrote:
On Tue, 12 Aug 2025 03:32:16 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 12/08/2025 1:50 am, john larkin wrote:
On Mon, 11 Aug 2025 07:27:37 -0700, Don Y
<blockedofcourse@foo.invalid> wrote:
On 8/11/2025 5:12 AM, BillGill wrote:
On 8/10/2025 9:27 AM, Don Y wrote:
<snip>
We design hardware that way. We seldom know or care about the >>>>>>>>>>>>>> internals of components. We design from data sheets or experiments andSince the inductors in your Spice simulations rarely have the data sheet
simulate using ideal components and encrypted behavioral models. >>>>>>>>>>>>>
parallel capacitance plugged into the Spice model of your inductor, you
clearly don't care as much as you should about the internals of at least
some of your components.
I care when it matters. Inductor SRF rarely does.
If you only design very slow stuff, that may be true.
20 GHz wideband e/o modulators with picosecond resolution timing >>>>>>>>>> generators is about our limit. We're getting lazy, I guess. >>>>>>>>>
for the 1 GHz stuff that I did forty years ago.
Distributed amplifier bias networks tend to use inductors. Some people >>>>>>>> like those dreadful conical things, but there are better ways. >>>>>>>>
Lots of people make conicals now that the Piconics patents have timed >>>>>>>> out.
I am aware that you do "design" fast stuff, though design doesn't seem
to be quite the right word for your approach.
I accept that we have different approaches to electronic design. My >>>>>>>> approach is to actually build stuff that works and sells.
So was mine, back when I could find people to hire me. The 1GHz stuff >>>>>>> ended up in a product Cambridge Instruments sold. I even got a patent >>>>>>> out of it.
"U.K. patent 2139411 "Moving Plate" (also US patent 4614872) on an >>>>>>> improved blanking system for charged particle beams, easily adjusted to >>>>>>> match a wide range of particle velocities; assigned to Cambridge >>>>>>> Instruments in 1983."
The boss wanted our voltage contrast electron microscope to be also >>>>>>> capable of EBIC (electron beam-induced current), so the beam-blanking >>>>>>> system had to cope with beam voltages from 15kV to 300V - blanking >>>>>>> plates long enough (18mm) to bend a 15kV had more than 0.5nsec transit >>>>>>> time for a 300V beam. If you could set the electrodes parallel to the >>>>>>> beam for the 15KV beam, and rotate them until they were at right angle >>>>>>> to beam for beam voltages less than about 800V you could shorten up the >>>>>>> region of interaction enough to stay out of trouble.
We did push the envelope a bit further than you seem to.
We did the picosecond master timing system and multi-GHz beam
modulators for the world's biggest laser. That was fun. The Livermore >>>>>> people are wonderful to work with. We always seemed to work with a >>>>>> genius female physicist who did the heavy thinking.
Of course your scheme was taken from the Hewlett-Packard Journal, and >>>>> made a lot more sense back when it was invented.
HP's vernier-locked digital delay generators and picosecond time
interval counters were big and clumsy, not worth copying. I'm not
aware that HP did any eo modulators.
Got references? Thought not.
It was you who made the claim, here, years ago.
I presume "big and clumsy and not worth copying" means that you tried >>>and failed.
No. The 5370 time interval counter and their time synthesizer box used
a triggered delay-line oscillator and a frequency heterodyne phase
locker. That was complex and had huge insertion delays and lots of
jitter.
Their (Keysights's) latest time interval counter has lots of jitter
too.
This summarizes known (to me) DDG architectures:
https://en.wikipedia.org/wiki/Digital_delay_generator#Design
I wrote that part.
Very interesting. How did Wavecrest's stuff do this?
Joe
On 8/11/2025 5:12 AM, BillGill wrote:
On 8/10/2025 9:27 AM, Don Y wrote:
<https://www.nytimes.com/2025/08/10/technology/coding-ai-jobs- students.html>I keep seeing that kids in high school (or even earlier) are being
And you wonder why your job is going away?a Hopefully, the end of
"Programmer" -- as a job description -- is just around the corner!
taught to code.a But then I have to wonder just what level of coding
that is. Do they actually learn programming, or do they just learn
to put together a bunch of stuff to create apps?
On Mon, 18 Aug 2025 21:08:56 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 18/08/2025 3:23 am, john larkin wrote:
On Mon, 18 Aug 2025 02:47:24 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 18/08/2025 1:31 am, john larkin wrote:
On Sun, 17 Aug 2025 14:35:04 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>> wrote:
On 17/08/2025 6:40 am, john larkin wrote:
On Sun, 17 Aug 2025 02:17:33 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>>> wrote:
On 13/08/2025 12:37 am, john larkin wrote:
On Tue, 12 Aug 2025 16:19:25 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 12/08/2025 9:19 am, john larkin wrote:
On Tue, 12 Aug 2025 03:32:16 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 12/08/2025 1:50 am, john larkin wrote:
On Mon, 11 Aug 2025 07:27:37 -0700, Don Y
<blockedofcourse@foo.invalid> wrote:
On 8/11/2025 5:12 AM, BillGill wrote:
On 8/10/2025 9:27 AM, Don Y wrote:
<snip>
We design hardware that way. We seldom know or care about the >>>>>>>>>>>>> internals of components. We design from data sheets or experiments andSince the inductors in your Spice simulations rarely have the data sheet
simulate using ideal components and encrypted behavioral models. >>>>>>>>>>>>
parallel capacitance plugged into the Spice model of your inductor, you
clearly don't care as much as you should about the internals of at least
some of your components.
I care when it matters. Inductor SRF rarely does.
If you only design very slow stuff, that may be true.
20 GHz wideband e/o modulators with picosecond resolution timing >>>>>>>>> generators is about our limit. We're getting lazy, I guess.
Scarcely a circuit which would use use much in the way of wound >>>>>>>> inductors - they might show up in the power supplies, but at 20GHz >>>>>>>> everything starts looking like a transmission line where the parallel >>>>>>>> capacitance is an integral part of the circuit. That was certainly true
for the 1 GHz stuff that I did forty years ago.
Distributed amplifier bias networks tend to use inductors. Some people >>>>>>> like those dreadful conical things, but there are better ways.
Lots of people make conicals now that the Piconics patents have timed >>>>>>> out.
I am aware that you do "design" fast stuff, though design doesn't seem >>>>>>>> to be quite the right word for your approach.
I accept that we have different approaches to electronic design. My >>>>>>> approach is to actually build stuff that works and sells.
So was mine, back when I could find people to hire me. The 1GHz stuff >>>>>> ended up in a product Cambridge Instruments sold. I even got a patent >>>>>> out of it.
"U.K. patent 2139411 "Moving Plate" (also US patent 4614872) on an >>>>>> improved blanking system for charged particle beams, easily adjusted to >>>>>> match a wide range of particle velocities; assigned to Cambridge
Instruments in 1983."
The boss wanted our voltage contrast electron microscope to be also >>>>>> capable of EBIC (electron beam-induced current), so the beam-blanking >>>>>> system had to cope with beam voltages from 15kV to 300V - blanking >>>>>> plates long enough (18mm) to bend a 15kV had more than 0.5nsec transit >>>>>> time for a 300V beam. If you could set the electrodes parallel to the >>>>>> beam for the 15KV beam, and rotate them until they were at right angle >>>>>> to beam for beam voltages less than about 800V you could shorten up the >>>>>> region of interaction enough to stay out of trouble.
We did push the envelope a bit further than you seem to.
We did the picosecond master timing system and multi-GHz beam
modulators for the world's biggest laser. That was fun. The Livermore >>>>> people are wonderful to work with. We always seemed to work with a
genius female physicist who did the heavy thinking.
Of course your scheme was taken from the Hewlett-Packard Journal, and
made a lot more sense back when it was invented.
HP's vernier-locked digital delay generators and picosecond time
interval counters were big and clumsy, not worth copying. I'm not
aware that HP did any eo modulators.
Got references? Thought not.
It was you who made the claim, here, years ago.
I presume "big and clumsy and not worth copying" means that you tried
and failed.
No. The 5370 time interval counter and their time synthesizer box used
a triggered delay-line oscillator and a frequency heterodyne phase
locker. That was complex and had huge insertion delays and lots of
jitter.
Their (Keysights's) latest time interval counter has lots of jitter
too.
This summarizes known (to me) DDG architectures:
https://en.wikipedia.org/wiki/Digital_delay_generator#Design
I wrote that part.
On Mon, 11 Aug 2025 12:19:35 -0700, Don Y
<blockedofcourse@foo.invalid> wrote:
On 8/11/2025 5:12 AM, BillGill wrote:
On 8/10/2025 9:27 AM, Don Y wrote:
<https://www.nytimes.com/2025/08/10/technology/coding-ai-jobs- students.html>I keep seeing that kids in high school (or even earlier) are being
And you wonder why your job is going away?-a Hopefully, the end of
"Programmer" -- as a job description -- is just around the corner!
taught to code.-a But then I have to wonder just what level of coding
that is. Do they actually learn programming, or do they just learn
to put together a bunch of stuff to create apps?
I meet CE/EE grads who don't know what a state machine is. Much less a software state machine.
On 19/08/2025 12:10 am, john larkin wrote:
On Mon, 18 Aug 2025 21:08:56 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 18/08/2025 3:23 am, john larkin wrote:
On Mon, 18 Aug 2025 02:47:24 +1000, Bill Sloman <bill.sloman@ieee.org> >>>> wrote:
On 18/08/2025 1:31 am, john larkin wrote:
On Sun, 17 Aug 2025 14:35:04 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>> wrote:
On 17/08/2025 6:40 am, john larkin wrote:
On Sun, 17 Aug 2025 02:17:33 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>>>> wrote:
On 13/08/2025 12:37 am, john larkin wrote:
On Tue, 12 Aug 2025 16:19:25 +1000, Bill Sloman <bill.sloman@ieee.org>Scarcely a circuit which would use use much in the way of wound >>>>>>>>> inductors - they might show up in the power supplies, but at 20GHz >>>>>>>>> everything starts looking like a transmission line where the parallel >>>>>>>>> capacitance is an integral part of the circuit. That was certainly true
wrote:
On 12/08/2025 9:19 am, john larkin wrote:
On Tue, 12 Aug 2025 03:32:16 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 12/08/2025 1:50 am, john larkin wrote:
On Mon, 11 Aug 2025 07:27:37 -0700, Don Y
<blockedofcourse@foo.invalid> wrote:
On 8/11/2025 5:12 AM, BillGill wrote:
On 8/10/2025 9:27 AM, Don Y wrote:
<snip>
We design hardware that way. We seldom know or care about the >>>>>>>>>>>>>> internals of components. We design from data sheets or experiments andSince the inductors in your Spice simulations rarely have the data sheet
simulate using ideal components and encrypted behavioral models. >>>>>>>>>>>>>
parallel capacitance plugged into the Spice model of your inductor, you
clearly don't care as much as you should about the internals of at least
some of your components.
I care when it matters. Inductor SRF rarely does.
If you only design very slow stuff, that may be true.
20 GHz wideband e/o modulators with picosecond resolution timing >>>>>>>>>> generators is about our limit. We're getting lazy, I guess. >>>>>>>>>
for the 1 GHz stuff that I did forty years ago.
Distributed amplifier bias networks tend to use inductors. Some people >>>>>>>> like those dreadful conical things, but there are better ways. >>>>>>>>
Lots of people make conicals now that the Piconics patents have timed >>>>>>>> out.
I am aware that you do "design" fast stuff, though design doesn't seem
to be quite the right word for your approach.
I accept that we have different approaches to electronic design. My >>>>>>>> approach is to actually build stuff that works and sells.
So was mine, back when I could find people to hire me. The 1GHz stuff >>>>>>> ended up in a product Cambridge Instruments sold. I even got a patent >>>>>>> out of it.
"U.K. patent 2139411 "Moving Plate" (also US patent 4614872) on an >>>>>>> improved blanking system for charged particle beams, easily adjusted to >>>>>>> match a wide range of particle velocities; assigned to Cambridge >>>>>>> Instruments in 1983."
The boss wanted our voltage contrast electron microscope to be also >>>>>>> capable of EBIC (electron beam-induced current), so the beam-blanking >>>>>>> system had to cope with beam voltages from 15kV to 300V - blanking >>>>>>> plates long enough (18mm) to bend a 15kV had more than 0.5nsec transit >>>>>>> time for a 300V beam. If you could set the electrodes parallel to the >>>>>>> beam for the 15KV beam, and rotate them until they were at right angle >>>>>>> to beam for beam voltages less than about 800V you could shorten up the >>>>>>> region of interaction enough to stay out of trouble.
We did push the envelope a bit further than you seem to.
We did the picosecond master timing system and multi-GHz beam
modulators for the world's biggest laser. That was fun. The Livermore >>>>>> people are wonderful to work with. We always seemed to work with a >>>>>> genius female physicist who did the heavy thinking.
Of course your scheme was taken from the Hewlett-Packard Journal, and >>>>> made a lot more sense back when it was invented.
HP's vernier-locked digital delay generators and picosecond time
interval counters were big and clumsy, not worth copying. I'm not
aware that HP did any eo modulators.
Got references? Thought not.
It was you who made the claim, here, years ago.
I presume "big and clumsy and not worth copying" means that you tried
and failed.
No. The 5370 time interval counter and their time synthesizer box used
a triggered delay-line oscillator and a frequency heterodyne phase
locker. That was complex and had huge insertion delays and lots of
jitter.
Their (Keysights's) latest time interval counter has lots of jitter
too.
This summarizes known (to me) DDG architectures:
https://en.wikipedia.org/wiki/Digital_delay_generator#Design
I wrote that part.
Not very well.
Instruments doesn't seem to fit into any of your schemes.
We used an 800MHz clock (phase locked to a 1OMHz crystal reference) as
our master clock and monitored any incoming start pulse by using it to
start a nominally 2.5nsec linear ramp, which was stopped on the next
clock edge and the end-of-ramp voltage digitised to give us a 5psec
accurate offset from the mater clock. We then counted 800Mz clock edges
to tell us when to start the ramp that triggered to output pulse when
the ramp hit the programmed voltage - again the step sizes were 5psec.
We could actually generate up to 1024 output pulses from one start
pulse, but the software guys never went for more than 128.
It took about 40nsec for the ECL arithmetic processor to program the
right voltage. The 800MHz master clock was crap, with about 60psec
jitter, but the shortest pulse we generated was 500psec wide, so it
didn't matter. We had ambitions of getting to 100psec, but we wouldn't
have had much trouble getting a better 800MHz clock if the project
hadn't been cancelled at the point where we had a couple of working >prototypes.
About ten years later, at Nijmegen University, I put together a detailed >study for a similar delay generator for an electron spin resonance >generator. That needed several moderately precisely timed pulses to set
up the microwave generator before you fired the precisely timed
microwave pulse the system needed.
The principle was much the same, but I used a 500MHz 1psec jitter master >clock based on a etched crystal, and got most of the fine delays out of an
https://www.onsemi.com/download/data-sheet/pdf/mc100ep195-d.pdfMC
That particular device wasn't around at the time, but its predecessor
was. We'd seen data sheets back in 1988, but no hardware.
The guy who wanted the system lost his funding before we could build
one. I'd used ECLinPS to clean up the system he already had, and that
had worked well enough to get him to want something better.
On Tue, 19 Aug 2025 17:12:05 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 19/08/2025 12:10 am, john larkin wrote:
On Mon, 18 Aug 2025 21:08:56 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 18/08/2025 3:23 am, john larkin wrote:
On Mon, 18 Aug 2025 02:47:24 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>> wrote:
On 18/08/2025 1:31 am, john larkin wrote:
On Sun, 17 Aug 2025 14:35:04 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>>> wrote:
On 17/08/2025 6:40 am, john larkin wrote:
On Sun, 17 Aug 2025 02:17:33 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 13/08/2025 12:37 am, john larkin wrote:
On Tue, 12 Aug 2025 16:19:25 +1000, Bill Sloman <bill.sloman@ieee.org>Scarcely a circuit which would use use much in the way of wound >>>>>>>>>> inductors - they might show up in the power supplies, but at 20GHz >>>>>>>>>> everything starts looking like a transmission line where the parallel
wrote:
On 12/08/2025 9:19 am, john larkin wrote:
On Tue, 12 Aug 2025 03:32:16 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 12/08/2025 1:50 am, john larkin wrote:
On Mon, 11 Aug 2025 07:27:37 -0700, Don Y
<blockedofcourse@foo.invalid> wrote:
On 8/11/2025 5:12 AM, BillGill wrote:
On 8/10/2025 9:27 AM, Don Y wrote:
<snip>
We design hardware that way. We seldom know or care about the >>>>>>>>>>>>>>> internals of components. We design from data sheets or experiments and
simulate using ideal components and encrypted behavioral models.
Since the inductors in your Spice simulations rarely have the data sheet
parallel capacitance plugged into the Spice model of your inductor, you
clearly don't care as much as you should about the internals of at least
some of your components.
I care when it matters. Inductor SRF rarely does.
If you only design very slow stuff, that may be true.
20 GHz wideband e/o modulators with picosecond resolution timing >>>>>>>>>>> generators is about our limit. We're getting lazy, I guess. >>>>>>>>>>
capacitance is an integral part of the circuit. That was certainly true
for the 1 GHz stuff that I did forty years ago.
Distributed amplifier bias networks tend to use inductors. Some people
like those dreadful conical things, but there are better ways. >>>>>>>>>
Lots of people make conicals now that the Piconics patents have timed >>>>>>>>> out.
I am aware that you do "design" fast stuff, though design doesn't seem
to be quite the right word for your approach.
I accept that we have different approaches to electronic design. My >>>>>>>>> approach is to actually build stuff that works and sells.
So was mine, back when I could find people to hire me. The 1GHz stuff >>>>>>>> ended up in a product Cambridge Instruments sold. I even got a patent >>>>>>>> out of it.
"U.K. patent 2139411 "Moving Plate" (also US patent 4614872) on an >>>>>>>> improved blanking system for charged particle beams, easily adjusted to
match a wide range of particle velocities; assigned to Cambridge >>>>>>>> Instruments in 1983."
The boss wanted our voltage contrast electron microscope to be also >>>>>>>> capable of EBIC (electron beam-induced current), so the beam-blanking >>>>>>>> system had to cope with beam voltages from 15kV to 300V - blanking >>>>>>>> plates long enough (18mm) to bend a 15kV had more than 0.5nsec transit >>>>>>>> time for a 300V beam. If you could set the electrodes parallel to the >>>>>>>> beam for the 15KV beam, and rotate them until they were at right angle >>>>>>>> to beam for beam voltages less than about 800V you could shorten up the
region of interaction enough to stay out of trouble.
We did push the envelope a bit further than you seem to.
We did the picosecond master timing system and multi-GHz beam
modulators for the world's biggest laser. That was fun. The Livermore >>>>>>> people are wonderful to work with. We always seemed to work with a >>>>>>> genius female physicist who did the heavy thinking.
Of course your scheme was taken from the Hewlett-Packard Journal, and >>>>>> made a lot more sense back when it was invented.
HP's vernier-locked digital delay generators and picosecond time
interval counters were big and clumsy, not worth copying. I'm not
aware that HP did any eo modulators.
Got references? Thought not.
It was you who made the claim, here, years ago.
I presume "big and clumsy and not worth copying" means that you tried
and failed.
No. The 5370 time interval counter and their time synthesizer box used
a triggered delay-line oscillator and a frequency heterodyne phase
locker. That was complex and had huge insertion delays and lots of
jitter.
Their (Keysights's) latest time interval counter has lots of jitter
too.
This summarizes known (to me) DDG architectures:
https://en.wikipedia.org/wiki/Digital_delay_generator#Design
I wrote that part.
Not very well.
You have a compulsive need to insult. It's obviously driven by a deep
feeling of inadequacy.
The electron-beam tester I put together at Cambridge
Instruments doesn't seem to fit into any of your schemes.
We used an 800MHz clock (phase locked to a 1OMHz crystal reference) as
our master clock and monitored any incoming start pulse by using it to
start a nominally 2.5nsec linear ramp, which was stopped on the next
clock edge and the end-of-ramp voltage digitised to give us a 5psec
accurate offset from the mater clock. We then counted 800Mz clock edges
to tell us when to start the ramp that triggered to output pulse when
the ramp hit the programmed voltage - again the step sizes were 5psec.
We could actually generate up to 1024 output pulses from one start
pulse, but the software guys never went for more than 128.
It took about 40nsec for the ECL arithmetic processor to program the
right voltage. The 800MHz master clock was crap, with about 60psec
jitter, but the shortest pulse we generated was 500psec wide, so it
didn't matter. We had ambitions of getting to 100psec, but we wouldn't
have had much trouble getting a better 800MHz clock if the project
hadn't been cancelled at the point where we had a couple of working
prototypes.
That's awfully complex.
Sounds expensive.
What was the minimum delay?
What was the jitter?
Minimum delay and low jitter are both selling points in a DDG. So is
cost.
Our first output edge from trigger rips through our board with just
prop delay. We get connector-to-connector minimum delays down to
around 20 ns.
About ten years later, at Nijmegen University, I put together a detailed
study for a similar delay generator for an electron spin resonance
generator. That needed several moderately precisely timed pulses to set
up the microwave generator before you fired the precisely timed
microwave pulse the system needed.
The principle was much the same, but I used a 500MHz 1psec jitter master
clock based on a etched crystal, and got most of the fine delays out of an >>
https://www.onsemi.com/download/data-sheet/pdf/mc100ep195-d.pdfMC
That particular device wasn't around at the time, but its predecessor
was. We'd seen data sheets back in 1988, but no hardware.
That part is expensive and awful. It's not accurate and has gobs of
jitter and temperature drift.
Fortunately, the 10EP195 is obsolete.
The guy who wanted the system lost his funding before we could build
one. I'd used ECLinPS to clean up the system he already had, and that
had worked well enough to get him to want something better.
ECL is a pain. We use some of the GigaComm parts when there is a
payoff, which is rare.
On 18/08/2025 1:31 am, john larkin wrote:
https://www.llnl.gov/article/48771/nif-welcomes-100000th-visitor
We're not sure which of us was actually # 100,000.
And why would you care?
On Mon, 18 Aug 2025 10:57:00 -0400, Joe Gwinn <joegwinn@comcast.net>
Very interesting. How did Wavecrest's stuff do this?
Joe
I'm not sure. I actually have an old/ebay Wavecrest but haven't taken
it apart.
I think they triggered a linear ramp and digitized that using a
clocked ADC.
ECL is a pain. We use some of the GigaComm parts when there is a
payoff, which is rare.
I meet CE/EE grads who don't know what a state machine is. Much less a software state machine.
I do love ECL, ever since the 100K family appeared.
Fast, clean supplies, clean impedances, controlled rise/fall times...
Not like that sh***y CMOS on steroids.
Around 1979, I built a-a real time signal averager that could
keep up with a TRW 8 bit 20 MHSPS ADC. The ADC was bleeding edge;
we got also a nekkid chip in an epoxy? cube, being a pilot customer.
You learn that when you write your 1st grammar parser
using YACC or bison.-a-a :-)
On 8/22/2025 1:57 AM, Gerhard Hoffmann wrote:
You learn that when you write your 1st grammar parser
using YACC or bison.-a-a :-)
But, we call them DFA/NFA -- something hardware people never
get exposed to.-a So, they don't think in terms of grammars
but, rather, just collections of states and events.-a It
makes documenting what the automaton is intended to do
considerably harder.-a Especially for anything beyond a
trivial machine (consider the state explosion problem that
you can "bury/hide" in a grammar)
[You can also get flex -- though not lex -- to build some
crude DFAs.-a And, any regex compiler.-a A *lot* closer to
self-documenting than anything you can build in hardware!]
Am 22.08.25 um 11:18 schrieb Don Y:
On 8/22/2025 1:57 AM, Gerhard Hoffmann wrote:
You learn that when you write your 1st grammar parser
using YACC or bison.-a-a :-)
But, we call them DFA/NFA -- something hardware people never
get exposed to.-a So, they don't think in terms of grammars
but, rather, just collections of states and events.-a It
makes documenting what the automaton is intended to do
considerably harder.-a Especially for anything beyond a
trivial machine (consider the state explosion problem that
you can "bury/hide" in a grammar)
[You can also get flex -- though not lex -- to build some
crude DFAs.-a And, any regex compiler.-a A *lot* closer to
self-documenting than anything you can build in hardware!]
Yes. That regular expressions / yacc / lex / awk stuff was
really meant to generate hardware state machines in
Weinberger arrays, a structure not unlike a PAL but not
user programmable.
The w in awk stands for Mr. Weinberger, the a for Mr. Aho,
the k for Mr. Kernighan, known for the C language,
The Unix group at Bell was a generation ahead, maybe two.
Am 19.08.25 um 13:09 schrieb john larkin:
ECL is a pain. We use some of the GigaComm parts when there is a
payoff, which is rare.
I do love ECL, ever since the 100K family appeared.
Fast, clean supplies, clean impedances, controlled rise/fall times...
Not like that sh***y CMOS on steroids.
Around 1979, I built a real time signal averager that could
keep up with a TRW 8 bit 20 MHSPS ADC. The ADC was bleeding edge;
we got also a nekkid chip in an epoxy? cube, being a pilot customer.
Stanford SR-620
On 8/22/2025 1:57 AM, Gerhard Hoffmann wrote:
You learn that when you write your 1st grammar parser
using YACC or bison.aa :-)
But, we call them DFA/NFA -- something hardware people never
get exposed to. So, they don't think in terms of grammars
but, rather, just collections of states and events. It
makes documenting what the automaton is intended to do
considerably harder. Especially for anything beyond a
trivial machine (consider the state explosion problem that
you can "bury/hide" in a grammar)
[You can also get flex -- though not lex -- to build some
crude DFAs. And, any regex compiler. A *lot* closer to
self-documenting than anything you can build in hardware!]
On Fri, 22 Aug 2025 09:54:05 +0200, Gerhard Hoffmann <dk4xp@arcor.de>
wrote:
Stanford SR-620
We use Keysight 53220s. They are OK but have a lot of jitter.
It would be fun to make a sub-ps jitter TIC, but I guess there's no
market.
I see parts, logic and oscillators, with fs jitter specs. I suppose
people use high-end oscilloscopes to measure them, or some indirect
trick.
Am 22.08.25 um 16:39 schrieb john larkin:
On Fri, 22 Aug 2025 09:54:05 +0200, Gerhard Hoffmann <dk4xp@arcor.de>
wrote:
Stanford SR-620
We use Keysight 53220s. They are OK but have a lot of jitter.
It would be fun to make a sub-ps jitter TIC, but I guess there's no
market.
I see parts, logic and oscillators, with fs jitter specs. I suppose
people use high-end oscilloscopes to measure them, or some indirect
trick.
What makes me really wonder with the SR-620: How can such a
small transformer feed that tablet of ECL!
Somehow all counters end at 5ps resolution.
I think it is harder than it looks at first sight.
pulse width / delay is relatively easy; it can be tested with 2
nearly synchronous oscillators with the second one sliding
next to the other over a span of several hours, but watch the
air conditioning. That is also ok for linearity versus phase.
For linearity vs. rise/fall times: I have no idea how to
guarantee that. Or temperature changes.
A little birdie told me yesterday that our ISS SPAD experiment
has seen first laser photons from the earth in the expected
ps window. :-)
Gerhard
On Fri, 22 Aug 2025 02:18:19 -0700, Don Y
<blockedofcourse@foo.invalid> wrote:
On 8/22/2025 1:57 AM, Gerhard Hoffmann wrote:
What's interesting is when input states can change any time, including
deep inside a clump of procedural state processing logic. That's a
classic hardware state machine hazard too.
< http://www.hoffmann-hochfrequenz.de/project_gallery/project_gallery.html -a-a >
On 8/22/2025 2:39 AM, Gerhard Hoffmann wrote:
Am 22.08.25 um 11:18 schrieb Don Y:
On 8/22/2025 1:57 AM, Gerhard Hoffmann wrote:
You learn that when you write your 1st grammar parser
using YACC or bison.-a-a :-)
But, we call them DFA/NFA -- something hardware people never
get exposed to.-a So, they don't think in terms of grammars
but, rather, just collections of states and events.-a It
makes documenting what the automaton is intended to do
considerably harder.-a Especially for anything beyond a
trivial machine (consider the state explosion problem that
you can "bury/hide" in a grammar)
[You can also get flex -- though not lex -- to build some
crude DFAs.-a And, any regex compiler.-a A *lot* closer to
self-documenting than anything you can build in hardware!]
Yes. That regular expressions / yacc / lex / awk stuff was
really meant to generate hardware state machines in
Weinberger arrays, a structure not unlike a PAL but not
user programmable.
The w in awk stands for Mr. Weinberger, the a for Mr. Aho,
the k for Mr. Kernighan, known for the C language,
The Unix group at Bell was a generation ahead, maybe two.
Amusing how uninspired names were (was the successor to C
going to be P?)
The beauty of encoding automata in grammars is how simply
(and completely) they can describe "everything" they are
intended to address.
On 19/08/2025 1:47 am, john larkin wrote:
On Mon, 11 Aug 2025 12:19:35 -0700, Don Y
<blockedofcourse@foo.invalid> wrote:
On 8/11/2025 5:12 AM, BillGill wrote:
On 8/10/2025 9:27 AM, Don Y wrote:
<https://www.nytimes.com/2025/08/10/technology/coding-ai-jobs-I keep seeing that kids in high school (or even earlier) are being
students.html>
And you wonder why your job is going away?-a Hopefully, the end of
"Programmer" -- as a job description -- is just around the corner!
taught to code.-a But then I have to wonder just what level of coding
that is. Do they actually learn programming, or do they just learn
to put together a bunch of stuff to create apps?
I meet CE/EE grads who don't know what a state machine is. Much less a
software state machine.
We had that trouble with Cambridge graduates. They knew their stuff, but
if you didn't ask the question using exactly the right jargon, they
didn't know what you meant. If you beat around the bush for a bit you
could mostly get them talking, but some of them were addicted to their specialist jargon, and wouldn't condescend to talk to people who didn't
use it.