From Newsgroup: sci.electronics.design

On 11/08/2025 7:25 pm, Niocl|iis|!n C||il|!n de Ghlost|-ir wrote:

On Mon, 11 Aug 2025, Bill Sloman wrote:
"On 11/08/2025 6:32 am, john larkin wrote:
[. . .]

Then why produce Verilog code?

True. Programmers should write everything in hex code, rather than using the crutch of assembler or some even higher level language."

Dear Doctor Sloman,

I believe that what Mister Larkin is getting at here, is that he wants to
use an AI at a higher level than Verilog, so Mister Larkin is perplexed as
to why Ben Cohen advocates an electronics worker to both use Perplexity AI
to produce Verilog code and to continue manually writing in Verilog.

That may be what he has in mind. He's not a subtle thinker, so he may
have missed the point that artificial intelligence isn't entirely
reliable, so the code it produces may not always work the way we'd like
it to.

Human designers have the same weakness - it often comes from having to
solve imperfectly specified problems.

Most of the requests for help we get here generate a lot of "what are
you actually trying to do" questions.

A good bit of real life electronics involves looking at other people's imperfectly document designs and working out how they were intended to
work, and why they went wrong in some specific unforeseen situation.
--
Bill Sloman, Sydney

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From Newsgroup: sci.electronics.design

On Mon, 11 Aug 2025 11:25:31 +0200, Nioclbis0n C<il0n de Ghlostoir <Spamassassin@irrt.De> wrote:

On Mon, 11 Aug 2025, Bill Sloman wrote:
"On 11/08/2025 6:32 am, john larkin wrote:
[. . .]

Then why produce Verilog code?

True. Programmers should write everything in hex code, rather than using the >crutch of assembler or some even higher level language."

Dear Mister Sloman,

I believe that what Mister Larkin is getting at here, is that he wants to >use an AI at a higher level than Verilog, so Mister Larkin is perplexed as >to why Ben Cohen advocates an electronics worker to both use Perplexity AI >to produce Verilog code and to continue manually writing in Verilog.

I'm not perplexed. I just think that there will eventually, maybe
soon, be better ways to design FPGAs than trying to define parallel
structures with hacked procedural languages.

It's the typing vs soldering thing again. Words vs images. Parallel
execution every clock vs the idea of a program counter executing at
some one location in a sea of object code.

When FPGAs were new, we designed with schematics. I design FPGAs on whiteboards now and let other people type the VHDL and do the test
benches. I suspect that's a common procedure: visual people design architectures and verbal people type it in.

LabView is awful, but something like that could design FPGAs.

The benefit of an intermediate VHDL/Verilog step would be code
portability.

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