From Newsgroup: sci.electronics.design

Hi

I am working on an application where I need pico second timing in a
power stage.

My go to controller, the STM32G071 only have 128MHz timer clock, and I
am running the stage at 250kHz, leaving 0.2%/8ns resolution on the duty
cycle.

I need more. I could use the STM32F334, which has picosecond timer,
using 144MHz timer clock followed by 217ps delay lines. But. it's 3 USD
in quantity.

Any other options that are low cost? (I guess FPGA's can do it, but none
comes close to much less than 3 USD)


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From Newsgroup: sci.electronics.design

Klaus Kragelund <klauskvik@hotmail.com> wrote:

Hi

I am working on an application where I need pico second timing in a
power stage.

My go to controller, the STM32G071 only have 128MHz timer clock, and I
am running the stage at 250kHz, leaving 0.2%/8ns resolution on the duty cycle.

I need more. I could use the STM32F334, which has picosecond timer,
using 144MHz timer clock followed by 217ps delay lines. But. it's 3 USD
in quantity.

Any other options that are low cost? (I guess FPGA's can do it, but none comes close to much less than 3 USD)

A 20-ns RC ramp driven by a separate CMOS buffer, with a level detector
made from a spare DAC channel and a FIN1002 line receiver.

We do that in our TDR and sampler offeringsrCowith two FIN1002s, the relative jitter is way down in the single-digit picoseconds.

Cheers

Phil Hobbs
--
Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC / Hobbs ElectroOptics Optics, Electro-optics, Photonics, Analog Electronics
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From Newsgroup: sci.electronics.design

Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:

Klaus Kragelund <klauskvik@hotmail.com> wrote:

Hi

I am working on an application where I need pico second timing in a
power stage.

My go to controller, the STM32G071 only have 128MHz timer clock, and I
am running the stage at 250kHz, leaving 0.2%/8ns resolution on the duty
cycle.

I need more. I could use the STM32F334, which has picosecond timer,
using 144MHz timer clock followed by 217ps delay lines. But. it's 3 USD
in quantity.

Any other options that are low cost? (I guess FPGA's can do it, but none
comes close to much less than 3 USD)

A 20-ns RC ramp driven by a separate CMOS buffer, with a level detector
made from a spare DAC channel and a FIN1002 line receiver.

We do that in our TDR and sampler offeringsrCowith two FIN1002s, the relative jitter is way down in the single-digit picoseconds.

A spare on-chip comparator channel might be good enough, depending on the requirements.

Cheers

Phil Hobbs
--
Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC / Hobbs ElectroOptics Optics, Electro-optics, Photonics, Analog Electronics
--- Synchronet 3.21a-Linux NewsLink 1.2

From Newsgroup: sci.electronics.design

On Sat, 30 Aug 2025 11:14:28 -0000 (UTC), Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:

Klaus Kragelund <klauskvik@hotmail.com> wrote:

Hi

I am working on an application where I need pico second timing in a
power stage.

My go to controller, the STM32G071 only have 128MHz timer clock, and I
am running the stage at 250kHz, leaving 0.2%/8ns resolution on the duty
cycle.

I need more. I could use the STM32F334, which has picosecond timer,
using 144MHz timer clock followed by 217ps delay lines. But. it's 3 USD
in quantity.

Any other options that are low cost? (I guess FPGA's can do it, but none
comes close to much less than 3 USD)

A 20-ns RC ramp driven by a separate CMOS buffer, with a level detector
made from a spare DAC channel and a FIN1002 line receiver.

We do that in our TDR and sampler offeringsuwith two FIN1002s, the relative >jitter is way down in the single-digit picoseconds.

Cheers

Phil Hobbs

We use FIN1101 as a 1 ns comparator. It's great. If the data sheet
said "comparator" it would cost five times as much.

LVDS's do have a lot if deliberate input offset, but that calibrates
out.

--- Synchronet 3.21a-Linux NewsLink 1.2

From Newsgroup: sci.electronics.design

On Sat, 30 Aug 2025 03:06:27 +0200, Klaus Kragelund
<klauskvik@hotmail.com> wrote:

Hi

I am working on an application where I need pico second timing in a
power stage.

My go to controller, the STM32G071 only have 128MHz timer clock, and I
am running the stage at 250kHz, leaving 0.2%/8ns resolution on the duty >cycle.

I need more. I could use the STM32F334, which has picosecond timer,
using 144MHz timer clock followed by 217ps delay lines. But. it's 3 USD
in quantity.

Any other options that are low cost? (I guess FPGA's can do it, but none >comes close to much less than 3 USD)

Why picoseconds in a power stage?

Can you dither it? We're doing that in a class-D amp to get around
some near-the-rail nonlinearities.

PID control loops will often dither themselves.

That STM has DACs and one of them could be used to improve PWM
resolution if you really need to.


--- Synchronet 3.21a-Linux NewsLink 1.2

From Newsgroup: sci.electronics.design

On 31/08/2025 2:05 am, john larkin wrote:

On Sat, 30 Aug 2025 03:06:27 +0200, Klaus Kragelund
<klauskvik@hotmail.com> wrote:

Hi

I am working on an application where I need pico second timing in a
power stage.

My go to controller, the STM32G071 only have 128MHz timer clock, and I
am running the stage at 250kHz, leaving 0.2%/8ns resolution on the duty
cycle.

I need more. I could use the STM32F334, which has picosecond timer,
using 144MHz timer clock followed by 217ps delay lines. But. it's 3 USD
in quantity.

Any other options that are low cost? (I guess FPGA's can do it, but none
comes close to much less than 3 USD)

Why picoseconds in a power stage?

If you are using mark-to-space to adjust output power, you can find you
need that to get fine control.

Can you dither it? We're doing that in a class-D amp to get around
some near-the-rail nonlinearities.

Dithering does work, but it works best if you are dithering between two
levels that are very close together.

PID control loops will often dither themselves.

But you don't want the output to move around much

That STM has DACs and one of them could be used to improve PWM
resolution if you really need to.

Really? The nice thing about PWM is that it's pretty efficient and you
don't have to cope with much waste heat.
--
Bill Sloman, Sydney
--- Synchronet 3.21a-Linux NewsLink 1.2

From Newsgroup: sci.electronics.design

On 30/08/2025 9:14 pm, Phil Hobbs wrote:

Klaus Kragelund <klauskvik@hotmail.com> wrote:

Hi

I am working on an application where I need pico second timing in a
power stage.

My go to controller, the STM32G071 only have 128MHz timer clock, and I
am running the stage at 250kHz, leaving 0.2%/8ns resolution on the duty
cycle.

I need more. I could use the STM32F334, which has picosecond timer,
using 144MHz timer clock followed by 217ps delay lines. But. it's 3 USD
in quantity.

Any other options that are low cost? (I guess FPGA's can do it, but none
comes close to much less than 3 USD)

A 20-ns RC ramp driven by a separate CMOS buffer, with a level detector
made from a spare DAC channel and a FIN1002 line receiver.

We do that in our TDR and sampler offeringsrCowith two FIN1002s, the relative jitter is way down in the single-digit picoseconds.

At Cambridge Instruments, around 1988, we used the middle 1.25nsec of a 2.50nsec ramp. The clock ran at 800MHz and the logic was Gigabit Logic's
GaAs parts, and we used broad-band transistors to make the ramp. It got auto-calibrated ever few minutes but that didn't take long, and we were ping-ponging between two parallel timers which over-lapped. The project
didn't make it to volume production, but we had several working
prototypes running well enough to demonstrate for about six months.

ECLinPS was almost as fast a few years later, and Motorola could make it
with a decent yield, which Gigabit never really mastered.
--
Bill Sloman, Sydney

--- Synchronet 3.21a-Linux NewsLink 1.2

From Newsgroup: sci.electronics.design

On 8/30/25 03:06, Klaus Kragelund wrote:

Hi

I am working on an application where I need pico second timing in a
power stage.

My go to controller, the STM32G071 only have 128MHz timer clock, and I
am running the stage at 250kHz, leaving 0.2%/8ns resolution on the duty cycle.

I need more. I could use the STM32F334, which has picosecond timer,
using 144MHz timer clock followed by 217ps delay lines. But. it's 3 USD
in quantity.

Any other options that are low cost? (I guess FPGA's can do it, but none comes close to much less than 3 USD) >

stm32g474 also hrtimer, afair ~180ps resolution. it is something like $3
in singles at jlcpcb, so I can't imagine they are anywhere hear $3 in
volume


--- Synchronet 3.21a-Linux NewsLink 1.2

From Newsgroup: sci.electronics.design

On 30/08/2025 23:24, Lasse Langwadt wrote:

On 8/30/25 03:06, Klaus Kragelund wrote:

Hi

I am working on an application where I need pico second timing in a
power stage.

My go to controller, the STM32G071 only have 128MHz timer clock, and I
am running the stage at 250kHz, leaving 0.2%/8ns resolution on the
duty cycle.

I need more. I could use the STM32F334, which has picosecond timer,
using 144MHz timer clock followed by 217ps delay lines. But. it's 3
USD in quantity.

Any other options that are low cost? (I guess FPGA's can do it, but
none comes close to much less than 3 USD) >

stm32g474 also hrtimer, afair ~180ps resolution. it is something like $3
in singles-a at jlcpcb, so I can't imagine they are anywhere hear $3 in volume

Yeah, I was looking at Western prices:

https://www.findchips.com/search/stm32g474

Volume price at LCSC is 2USD:

https://www.lcsc.com/search?q=stm32g474&s_z=n_stm32g474

--- Synchronet 3.21a-Linux NewsLink 1.2

From Newsgroup: sci.electronics.design

On 30/08/2025 13:14, Phil Hobbs wrote:

Klaus Kragelund <klauskvik@hotmail.com> wrote:

Hi

I am working on an application where I need pico second timing in a
power stage.

My go to controller, the STM32G071 only have 128MHz timer clock, and I
am running the stage at 250kHz, leaving 0.2%/8ns resolution on the duty
cycle.

I need more. I could use the STM32F334, which has picosecond timer,
using 144MHz timer clock followed by 217ps delay lines. But. it's 3 USD
in quantity.

Any other options that are low cost? (I guess FPGA's can do it, but none
comes close to much less than 3 USD)

A 20-ns RC ramp driven by a separate CMOS buffer, with a level detector
made from a spare DAC channel and a FIN1002 line receiver.

We do that in our TDR and sampler offeringsrCowith two FIN1002s, the relative jitter is way down in the single-digit picoseconds.

Nice idea, it could even be done with a second PWM channel, to avoid the
need for a DAC. In any case it needs a good stable supply for the buffer.

The micro I have has a 20ns comparator, but that's much too slow for
this addition

The FIN1002 is 20 cents at LCSC

Did a quick simulation:

www.electronicsdesign.dk/SED/highrespwm.pdf

The transfer function from the DAC to the PWM is logaritmic, so like you
say need to do calibration, or alternatively switch to a current source feeding into a capacitor. However, a current source with 10ns compliance
is not that easy, easier with the RC
--- Synchronet 3.21a-Linux NewsLink 1.2

From Newsgroup: sci.electronics.design

On 30/08/2025 18:05, john larkin wrote:

On Sat, 30 Aug 2025 03:06:27 +0200, Klaus Kragelund
<klauskvik@hotmail.com> wrote:

Hi

I am working on an application where I need pico second timing in a
power stage.

My go to controller, the STM32G071 only have 128MHz timer clock, and I
am running the stage at 250kHz, leaving 0.2%/8ns resolution on the duty
cycle.

I need more. I could use the STM32F334, which has picosecond timer,
using 144MHz timer clock followed by 217ps delay lines. But. it's 3 USD
in quantity.

Any other options that are low cost? (I guess FPGA's can do it, but none
comes close to much less than 3 USD)

Why picoseconds in a power stage?

Can you dither it? We're doing that in a class-D amp to get around
some near-the-rail nonlinearities.

PID control loops will often dither themselves.

That STM has DACs and one of them could be used to improve PWM
resolution if you really need to.

I could possibly do dithering. This is for a halfbridge stage feeding
current into a battery. The battery voltage is solid, so need high
resolution of the output PWM to get good accuracy on the charging current.

Could add a LC filter with larger output capacitors to bring the cutoff frequency down, allowing for dithering, but trying to reduce cost, thus minimum capacitor size that the ripple current allows for.

Noise in the system will probably result in some dithering anyway,
coming from quantization of the current measurement.

Since the battery voltage is solid, I have turned down the integration
gain of the compensator, and then running an outer current loop to
regulate the PWM.
--- Synchronet 3.21a-Linux NewsLink 1.2

From Newsgroup: sci.electronics.design

On Sun, 31 Aug 2025 13:42:55 +0200, Klaus Kragelund
<klauskvik@hotmail.com> wrote:

On 30/08/2025 18:05, john larkin wrote:

On Sat, 30 Aug 2025 03:06:27 +0200, Klaus Kragelund
<klauskvik@hotmail.com> wrote:

Hi

I am working on an application where I need pico second timing in a
power stage.

My go to controller, the STM32G071 only have 128MHz timer clock, and I
am running the stage at 250kHz, leaving 0.2%/8ns resolution on the duty
cycle.

I need more. I could use the STM32F334, which has picosecond timer,
using 144MHz timer clock followed by 217ps delay lines. But. it's 3 USD
in quantity.

Any other options that are low cost? (I guess FPGA's can do it, but none >>> comes close to much less than 3 USD)

Why picoseconds in a power stage?

Can you dither it? We're doing that in a class-D amp to get around
some near-the-rail nonlinearities.

PID control loops will often dither themselves.

That STM has DACs and one of them could be used to improve PWM
resolution if you really need to.

I could possibly do dithering. This is for a halfbridge stage feeding >current into a battery. The battery voltage is solid, so need high >resolution of the output PWM to get good accuracy on the charging current.

Could add a LC filter with larger output capacitors to bring the cutoff >frequency down, allowing for dithering, but trying to reduce cost, thus >minimum capacitor size that the ripple current allows for.

Noise in the system will probably result in some dithering anyway,
coming from quantization of the current measurement.

Yes. I did a bunch (sold tens of thousands) of electric meters that
used a single-slope 7-bit ADC to get infinite current sensor
resolution. Just added a triangle to the current transformer signal,
which smeared out a few LSBs.

Since the battery voltage is solid, I have turned down the integration
gain of the compensator, and then running an outer current loop to
regulate the PWM.

0.2% isn't enough resolution for a battery?

If the loop is PID, the output must average exact. It will dither
itself as needed.

Or, add a few LSBs of gaussian or pseudorandom noise to the PWM, and
that will smear the quantization and make things linear to below an
LSB.

Over the top, just for fun, delta-sigma the LSB to get, say, 32 bit
resolution.

All those are pretty much equivalent. Batteries aren't very wideband
devices.

--- Synchronet 3.21a-Linux NewsLink 1.2

From Newsgroup: sci.electronics.design

On 31/08/2025 16:46, john larkin wrote:

On Sun, 31 Aug 2025 13:42:55 +0200, Klaus Kragelund
<klauskvik@hotmail.com> wrote:

On 30/08/2025 18:05, john larkin wrote:

On Sat, 30 Aug 2025 03:06:27 +0200, Klaus Kragelund
<klauskvik@hotmail.com> wrote:

Hi

I am working on an application where I need pico second timing in a
power stage.

My go to controller, the STM32G071 only have 128MHz timer clock, and I >>>> am running the stage at 250kHz, leaving 0.2%/8ns resolution on the duty >>>> cycle.

I need more. I could use the STM32F334, which has picosecond timer,
using 144MHz timer clock followed by 217ps delay lines. But. it's 3 USD >>>> in quantity.

Any other options that are low cost? (I guess FPGA's can do it, but none >>>> comes close to much less than 3 USD)

Why picoseconds in a power stage?

Can you dither it? We're doing that in a class-D amp to get around
some near-the-rail nonlinearities.

PID control loops will often dither themselves.

That STM has DACs and one of them could be used to improve PWM
resolution if you really need to.

I could possibly do dithering. This is for a halfbridge stage feeding
current into a battery. The battery voltage is solid, so need high
resolution of the output PWM to get good accuracy on the charging current. >>
Could add a LC filter with larger output capacitors to bring the cutoff
frequency down, allowing for dithering, but trying to reduce cost, thus
minimum capacitor size that the ripple current allows for.

Noise in the system will probably result in some dithering anyway,
coming from quantization of the current measurement.

Yes. I did a bunch (sold tens of thousands) of electric meters that
used a single-slope 7-bit ADC to get infinite current sensor
resolution. Just added a triangle to the current transformer signal,
which smeared out a few LSBs.

Since the battery voltage is solid, I have turned down the integration
gain of the compensator, and then running an outer current loop to
regulate the PWM.

0.2% isn't enough resolution for a battery?

The input voltage to the buck is 48V, so the resolution at 0.2% equates
to 0.1V discrete steps. The internal resistance of the battery is 4mohm, resulting in current resolution of 25A.

I need of course to add lead resistances, and my current sense of 1mohm,
but it's still way above what I need. I would expect to be able to
control the current in 100mA steps.

If the loop is PID, the output must average exact. It will dither
itself as needed.

Or, add a few LSBs of gaussian or pseudorandom noise to the PWM, and
that will smear the quantization and make things linear to below an
LSB.

Over the top, just for fun, delta-sigma the LSB to get, say, 32 bit resolution.

All those are pretty much equivalent. Batteries aren't very wideband
devices.

--- Synchronet 3.21a-Linux NewsLink 1.2

From Newsgroup: sci.electronics.design

On 31/08/2025 22:35, Klaus Kragelund wrote:

On 31/08/2025 16:46, john larkin wrote:

On Sun, 31 Aug 2025 13:42:55 +0200, Klaus Kragelund
<klauskvik@hotmail.com> wrote:

On 30/08/2025 18:05, john larkin wrote:

On Sat, 30 Aug 2025 03:06:27 +0200, Klaus Kragelund
<klauskvik@hotmail.com> wrote:

Hi

I am working on an application where I need pico second timing in a
power stage.

My go to controller, the STM32G071 only have 128MHz timer clock, and I >>>>> am running the stage at 250kHz, leaving 0.2%/8ns resolution on the
duty
cycle.

I need more. I could use the STM32F334, which has picosecond timer,
using 144MHz timer clock followed by 217ps delay lines. But. it's 3 >>>>> USD
in quantity.

Any other options that are low cost? (I guess FPGA's can do it, but >>>>> none
comes close to much less than 3 USD)

Why picoseconds in a power stage?

Can you dither it? We're doing that in a class-D amp to get around
some near-the-rail nonlinearities.

PID control loops will often dither themselves.

That STM has DACs and one of them could be used to improve PWM
resolution if you really need to.

I could possibly do dithering. This is for a halfbridge stage feeding
current into a battery. The battery voltage is solid, so need high
resolution of the output PWM to get good accuracy on the charging
current.

Could add a LC filter with larger output capacitors to bring the cutoff
frequency down, allowing for dithering, but trying to reduce cost, thus
minimum capacitor size that the ripple current allows for.

Noise in the system will probably result in some dithering anyway,
coming from quantization of the current measurement.

Yes. I did a bunch (sold tens of thousands) of electric meters that
used a single-slope 7-bit ADC to get infinite current sensor
resolution. Just added a triangle to the current transformer signal,
which smeared out a few LSBs.

Since the battery voltage is solid, I have turned down the integration
gain of the compensator, and then running an outer current loop to
regulate the PWM.

0.2% isn't enough resolution for a battery?

The input voltage to the buck is 48V, so the resolution at 0.2% equates
to 0.1V discrete steps. The internal resistance of the battery is 4mohm, resulting in current resolution of 25A.

I need of course to add lead resistances, and my current sense of 1mohm,
but it's still way above what I need. I would expect to be able to
control the current in 100mA steps.

If the loop is PID, the output must average exact. It will dither
itself as needed.

Or, add a few LSBs of gaussian or pseudorandom-a noise to the PWM, and
that will smear the quantization and make things linear to below an
LSB.

Over the top, just for fun, delta-sigma the LSB to get, say, 32 bit
resolution.

All those are pretty much equivalent. Batteries aren't very wideband
devices.

One side effect of this, is how the controller is actually started. If
the setpoint (duty cycle times input voltage) is different than the
battery voltage, a large current will flow.

For example, the BQ25756 charge controller:

https://www.ti.com/lit/ds/symlink/bq25756.pdf

Looks like they are doing a current mode loop, so cycle per cycle peak
current control, so they do not apply/guess a duty cycle, they ramp the reference up very slowly in the current loop, to avoid setting a duty cycle.


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