From Newsgroup: comp.lang.forth

Now riscv is the future.

I don't know. From what I learned, RISC-V
is strongly compiler-oriented. They wrote,
for example, that it lacks any condition codes.
Only conditional branches are predicated on
examining the contents of registers at the time
of the branch. No "add with carry" nor "subtract
with carry". From an assembly point of view, the
lack of a carry flag is a PITA if you desire to
do multi-word mathematical manipulation of numbers.

So it seems, that the RISC-V architecture is intended
to be used by compilers generating code from high level
languages. Therefore I rather still prefer that "closed"
ARM arch. Besides: it's more ubiquitous and cheaper.

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From Newsgroup: comp.lang.forth

Am 15.07.2025 um 17:25 schrieb LIT:

Now riscv is the future.

I don't know. From what I learned, RISC-V
is strongly compiler-oriented. They wrote,
for example, that it lacks any condition codes.
Only conditional branches are predicated on
examining the contents of registers at the time
of the branch. No "add with carry" nor "subtract
with carry". From an assembly point of view, the
lack of a carry flag is a PITA if you desire to
do multi-word mathematical manipulation of numbers.

So it seems, that the RISC-V architecture is intended
to be used by compilers generating code from high level
languages.

I read somewhere:
The standard is now managed by RISC-V International, which
has more than 3,000 members and which reported that more
than 10 billion chips containing RISC-V cores had shipped
by the end of 2022. Many implementations of RISC-V are
available, both as open-source cores and as commercial
IP products.

You call that compiler-oriented???


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From Newsgroup: comp.lang.forth

On 16/07/2025 12:09 pm, minforth wrote:

Am 15.07.2025 um 17:25 schrieb LIT:

Now riscv is the future.

I don't know. From what I learned, RISC-V
is strongly compiler-oriented. They wrote,
for example, that it lacks any condition codes.
Only conditional branches are predicated on
examining the contents of registers at the time
of the branch. No "add with carry" nor "subtract
with carry". From an assembly point of view, the
lack of a carry flag is a PITA if you desire to
do multi-word mathematical manipulation of numbers.

So it seems, that the RISC-V architecture is intended
to be used by compilers generating code from high level
languages.

I read somewhere:
The standard is now managed by RISC-V International, which
has more than 3,000 members and which reported that more
than 10 billion chips containing RISC-V cores had shipped
by the end of 2022. Many implementations of RISC-V are
available, both as open-source cores and as commercial
IP products.

You call that compiler-oriented???

It depends on how many are being programmed by the likes of GCC.
When ATMEL hit the market the manufacturer claimed their chips
were designed with compilers in mind. Do Arduino users program
in hand-coded assembler? Do you? It's no longer just the chip's
features and theoretical performance one has to worry about but
the compilers too.

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From Newsgroup: comp.lang.forth

Am 16.07.2025 um 07:21 schrieb dxf:

On 16/07/2025 12:09 pm, minforth wrote:

Am 15.07.2025 um 17:25 schrieb LIT:

Now riscv is the future.

I don't know. From what I learned, RISC-V
is strongly compiler-oriented. They wrote,
for example, that it lacks any condition codes.
Only conditional branches are predicated on
examining the contents of registers at the time
of the branch. No "add with carry" nor "subtract
with carry". From an assembly point of view, the
lack of a carry flag is a PITA if you desire to
do multi-word mathematical manipulation of numbers.

So it seems, that the RISC-V architecture is intended
to be used by compilers generating code from high level
languages.

I read somewhere:
The standard is now managed by RISC-V International, which
has more than 3,000 members and which reported that more
than 10 billion chips containing RISC-V cores had shipped
by the end of 2022. Many implementations of RISC-V are
available, both as open-source cores and as commercial
IP products.

You call that compiler-oriented???

It depends on how many are being programmed by the likes of GCC.
When ATMEL hit the market the manufacturer claimed their chips
were designed with compilers in mind. Do Arduino users program
in hand-coded assembler? Do you? It's no longer just the chip's
features and theoretical performance one has to worry about but
the compilers too.

Don't worry, be happy, visit https://riscv.org/

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From Newsgroup: comp.lang.forth

It depends on how many are being programmed by the likes of GCC.
When ATMEL hit the market the manufacturer claimed their chips
were designed with compilers in mind. Do Arduino users program
in hand-coded assembler? Do you? It's no longer just the chip's
features and theoretical performance one has to worry about but
the compilers too.

Regarding features it's worth to mention
that ATMELs actually are quite nice to
program them in ML. Even, if they were
designed "with compilers in mind".

But when CPU is stripped off SBC/ADC and
similar... I don't know.

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From Newsgroup: comp.lang.forth

Now riscv is the future.

I don't know. From what I learned, RISC-V
is strongly compiler-oriented. They wrote,
for example, that it lacks any condition codes.
Only conditional branches are predicated on
examining the contents of registers at the time
of the branch. No "add with carry" nor "subtract
with carry". From an assembly point of view, the
lack of a carry flag is a PITA if you desire to
do multi-word mathematical manipulation of numbers.

So it seems, that the RISC-V architecture is intended
to be used by compilers generating code from high level
languages.

I read somewhere:
The standard is now managed by RISC-V International, which
has more than 3,000 members and which reported that more
than 10 billion chips containing RISC-V cores had shipped
by the end of 2022. Many implementations of RISC-V are
available, both as open-source cores and as commercial
IP products.

You call that compiler-oriented???

I think it doesn't depend on RISCV members count,
but on technical specs/abilities of CPU rather.
Like on the ones I listed, for instance.

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From Newsgroup: comp.lang.forth

On 16/07/2025 6:25 pm, LIT wrote:

It depends on how many are being programmed by the likes of GCC.
When ATMEL hit the market the manufacturer claimed their chips
were designed with compilers in mind.-a Do Arduino users program
in hand-coded assembler?-a Do you?-a It's no longer just the chip's
features and theoretical performance one has to worry about but
the compilers too.

Regarding features it's worth to mention
that ATMELs actually are quite nice to
program them in ML. Even, if they were
designed "with compilers in mind".
...

Reminds me of the 6502 for some reason. But it's the 'skip next
instruction on bit in register' that throws me. Not to mention
companies that release chips that don't do what the spec says.
Their solution? Amend the documentation to exclude that feature!

Didn't get that in the good old days as products were expected to
have a reasonable lifetime. Today CPU designs are as 'throw away'
as everything else. No reason to believe RISC-V will be different.
Only thing distinguishing it are the years of hype and promise.

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From Newsgroup: comp.lang.forth

Reminds me of the 6502 for some reason. But it's the 'skip next
instruction on bit in register' that throws me.

Nothing too unusual. It's actually just an abbreviation
for something like, for example:

CMP AX, BX
JZ SHORT skip
CALL something
skip: ...

So instead of separate CMP and JZ we've got
"CMP?JZ" as single instruction. If not the
variable size of instruction in x86, one could
devise a macro. On a second thought: probably
in A86 it'll be possible to devise such a macro,
because its macro facility treats macro
parameters character-wise. So probably a macro
like 'CMP?JZ reg1,reg2 next_instruction" should
be possible (I'll try that later).

PIC features similar instructions (INCFSZ/DECFSZ).
PIC is actually more 6502-like, with its spartan
instruction set (when compared to ATMEL).

Didn't get that in the good old days as products were expected to
have a reasonable lifetime. Today CPU designs are as 'throw away'
as everything else. No reason to believe RISC-V will be different.
Only thing distinguishing it are the years of hype and promise.

Well, at least x86 and ARM seem to be more 'persistent'.
Actually they already proved to be.

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