From Newsgroup: comp.arch

Some additional tweaks have been made to the Concertina II instruction set.

The Type I header has had one capability removed from it in order to make
room for the Type Ia header.

Now, in addition to a zero-overhead header which has an operate
instruction built in, zero-overhead headers which have a memory-reference instruction built in are also available.

The format of those memory-reference instructions is extremely limited,
but at least it makes it _possible_ to have pseudo-immediates in a
sequence where a memory-reference instruction goes in the leading spot of
the block involved. One just has to allocate registers correctly to get
this zero reference.

Also, a while back, the ability to have 64-bit instructions in code
without block headers was removed. It wasn't intneded to actually remove
this from the ISA, but at the time, significant changes and re-
organizations of the block headers were taking place, and I didn't want to keep these instructions updated to correspond.

Now that this phase is over, they have been put back in.

These changes, and some recent ones preceding them, have been aimed at enhancing either the ability to do without headers, or, if headers are
needed, to increase the options to avoid their overhead cost if possible.

Block headers are needed, because I can't figure out how to do pseudo- immediates without them, but as they are painful, I'm trying to both
minimize their overhead and reduce the number of cases where there is need
for them as much as I can.

John Savard
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