On Wed, 07 May 2025 19:21:20 -0700, john larkin <jl@glen--canyon.com>
wrote:

On Wed, 7 May 2025 20:27:58 -0400, bitrex <user@example.net> wrote:

On 5/7/2025 4:01 PM, john larkin wrote:

On Wed, 7 May 2025 20:32:41 +0100, Martin Brown
<'''newspam'''@nonad.co.uk> wrote:

On 06/05/2025 16:48, john larkin wrote:

A DDS clock generator uses an NCO (a phase accumulator) and takes some >>>>> number of MSBs, maps through a sine lookup table, drives a DAC and a >>>>> lowpass filter and finally a comparator. The DAC output gets pretty
ratty near Nyquist, and the filter smooths out and interpolates the
steps and reduces jitter.

But why do the sine lookup? Why not use the phase accumulator MSBs
directly and get a sawtooth, and filter that?

A saw tooth wave has a huge step like discontinuity in it which looks
very ugly in the frequency domain with strong harmonics. Strong sharp
features in time domain are broad in frequency space and vice versa.

If you wanted something a bit different then detecting the phase
accumulator overflow and reversing the count sense to get a triangle
wave might be an option (at half the frequency). Needs some very careful >>>> maths at the boundary flips to avoid introducing jitter.

From that triangle wave you can use HP's wizard diode shaping network >>>> trick to get a pretty good clean sine wave.

Yes, a triangle would be better than a sawtooth... fewer nasty
subharmonics. But we may as well stick with the classic boring sine
wave. The sine lookup is trivial in an FPGA.

A band-limited square wave is pretty space & computation-efficient, you >>just store the Gibbs phenomena portion of the wave to whatever harmonic >>level you desire, play it back, and then sit there and wait during the
DC parts of the wave.

If you then integrate a band-limited square wave you get a band-limited >>triangle wave directly.

If I could make a square wave from the MSBs of the phase accumulator,
I might not need the DAC and filter and comparator.

Just using the MSB of the phase accumulator is the right frequency,
but it's very jitterey.

So, is there a way to examine some number of MSBs and make an edge
with high time resolution, all digitally, all inside the FPGA? To even
1 clock resolution, preferably better?

There probably is.

We discussed exactly this issue in August 2022 in the thread "Re:
Direct digital synthesis of square waves". My posting on 18 August
about "bottom bits" is one way.

Joe

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