mitchalsup@aol.com (MitchAlsup1) writes:
Let us consider a device down on the PCIe tree and it sends up a
DMA request. The device can manage a large number of outstanding
commands to a single process or to multiple different processes.
{{Same problem for interrupts and ATS requests}}
DMA from device Bus;Device,function arrives at the HostBridge.
The Memory read and write TLPs do not identify the source
function using the configuration address (BDF). Those
TLPs contain the target address. The PCIe controller
will construct a target RID (Segment + BDF) to pass to the
IOMMU based on the port upon which the request was
received (and the captured bus number from the target).
Config Read and Config Write TLPs have both the target and
source RIDs (routing IDs) in the TLP, although depending
on type 0 or type 1, they may not contain the full RID,
but only the dev/func (or just func for ARI endpoints).
What part of the PCIe message identifies which command this
PCIe message is for (since the device can have a large number
of commands outstanding) ?
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