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I usually (and simplistically) divide CPU designs (implementations) into
two main categories:
- Pipelined
- Non-pipelined
Of course, there is a sliding scale at play, but let's not get into that debate.
My question is: What is the best name for non-pipelined designs?
I'm thinking about CPU:s that transition through several states (one
clock cycle after another) when executing a single instruction (e.g.
FETCH + DECODE + EXECUTE), and where instruction and data typically
share the same memory interface.
/Marcus
Why, in this day and age, would anyone want to even consider doing
something less pipelined than that ?!?!?
On Sun, 8 Dec 2024 23:05:40 +0000, MitchAlsup1 wrote:
Why, in this day and age, would anyone want to even consider doing
something less pipelined than that ?!?!?
Here’s one reason (tell me if I’m wrong): I remember some CPU designs used
CMOS and probably some other hardware magic I don’t understand to create chips that could run at any speed down to 0Hz.
On Sun, 8 Dec 2024 23:05:40 +0000, MitchAlsup1 wrote:
Why, in this day and age, would anyone want to even consider doing
something less pipelined than that ?!?!?
Here’s one reason (tell me if I’m wrong): I remember some CPU designs used CMOS and probably some other hardware magic I don’t understand to create > chips that could run at any speed down to 0Hz.
That is, you could slow down the clock and even stop it completely at
any point in instruction execution (keep the power on) to pause the
program, then start it up again and the program would resume from that
point.
Would that work with a pipeline? Actually I suppose it would.
On Sun, 8 Dec 2024 22:10:15 +0000, Marcus wrote:
I usually (and simplistically) divide CPU designs (implementations) into
two main categories:
- Pipelined
- Non-pipelined
Of course, there is a sliding scale at play, but let's not get into that
debate.
My question is: What is the best name for non-pipelined designs?
If any portion of the design fetches the next instruction before the
last calculation of the previous instruction, then the design is
pipelined. CDC 6600 had a pipelined front end and serially reusable calculation units. {{Also note under this definition 6800, 68000, and
8086 were (partially pipelined) architectures.
I'm thinking about CPU:s that transition through several states (one
clock cycle after another) when executing a single instruction (e.g.
FETCH + DECODE + EXECUTE), and where instruction and data typically
share the same memory interface.
Given that one can take an off the shelf (rather cheap) FPGA and
implement a fully pipeline RISC ISA implementation::
Why, in this day and age, would anyone want to even consider doing
something less pipelined than that ?!?!?
On 2024-12-09 00:05, MitchAlsup1 wrote:
On Sun, 8 Dec 2024 22:10:15 +0000, Marcus wrote:
I usually (and simplistically) divide CPU designs (implementations) into >>> two main categories:
- Pipelined
- Non-pipelined
Of course, there is a sliding scale at play, but let's not get into that >>> debate.
My question is: What is the best name for non-pipelined designs?
If any portion of the design fetches the next instruction before the
last calculation of the previous instruction, then the design is
pipelined. CDC 6600 had a pipelined front end and serially reusable
calculation units. {{Also note under this definition 6800, 68000, and
8086 were (partially pipelined) architectures.
Yes, it's certainly a scale, where most implementations have *some* pipelining and *some* unit reuse. I'm thinking about what to call the
two ends of that scale.
I'm thinking about CPU:s that transition through several states (one
clock cycle after another) when executing a single instruction (e.g.
FETCH + DECODE + EXECUTE), and where instruction and data typically
share the same memory interface.
Given that one can take an off the shelf (rather cheap) FPGA and
implement a fully pipeline RISC ISA implementation::
Why, in this day and age, would anyone want to even consider doing
something less pipelined than that ?!?!?
My question is more about the nomenclature, not about merits of
different design choices.
It's mostly about overall design, where on one end (e.g. the MIPS)
you focus on instruction throughput at the cost of resource duplication, while on the other end (e.g. 6502) you focus on resource reuse at the
cost of lower performance.
/Marcus
According to my understanding of “pipelined” most designs are
pipelined. There are not very many non-pipelined designs.
Non-pipelined
designs perform everything in one long clock cycle.
Robert Finch <robfi680@gmail.com> schrieb:
According to my understanding of “pipelined” most designs are
pipelined. There are not very many non-pipelined designs.
Not any more.
Non-pipelined
designs perform everything in one long clock cycle.
Earlier architectures had several clock cycles per instruction,
also without pipelining. I think the single-clock CPUs mostly
serve as an example for educational purposes.
Thomas Koenig wrote:
Robert Finch <robfi680@gmail.com> schrieb:
According to my understanding of “pipelined” most designs are
pipelined. There are not very many non-pipelined designs.
Not any more.
Non-pipelined
designs perform everything in one long clock cycle.
Earlier architectures had several clock cycles per instruction,
also without pipelining. I think the single-clock CPUs mostly
serve as an example for educational purposes.
It is possible to do everything for a risc style ISA in one clock but
it would need a Harvard architecture with separate instruction and
data memory because it would have to read the instruction memory and
also LD [reg]->reg or ST reg->[reg] data memory within the same clock.
So the only flip-flops would be in the 3-port register file and
the RIP register, and everything between instruction read and result
write is combinatorial logic. The critical timing path would be
2x the mem access time plus combinatorial logic.
On Thu, 26 Dec 2024 18:54:42 +0000, EricP wrote:
Thomas Koenig wrote:
Robert Finch <robfi680@gmail.com> schrieb:
According to my understanding of “pipelined” most designs are
pipelined. There are not very many non-pipelined designs.
Not any more.
Non-pipelined
designs perform everything in one long clock cycle.
Earlier architectures had several clock cycles per instruction,
also without pipelining. I think the single-clock CPUs mostly
serve as an example for educational purposes.
It is possible to do everything for a risc style ISA in one clock but
??? LDs in 1 cycle
??? IMUL in 1 cycle
??? IDIV in 1 cycle
??? L1 miss in 1 cycle
??? FP <any> in 1 cycle
it would need a Harvard architecture with separate instruction and
data memory because it would have to read the instruction memory and
also LD [reg]->reg or ST reg->[reg] data memory within the same clock.
So the only flip-flops would be in the 3-port register file and
the RIP register, and everything between instruction read and result
write is combinatorial logic. The critical timing path would be
2x the mem access time plus combinatorial logic.