On Thu, 31 Oct 2024 9:18:37 +0000, Robert Finch wrote:

Thinking about organizing a cache controller to fetch an entire 4kB page
of memory at a time on a cache miss. The reason being the memory system
is tremendously faster than the CPU clock as long as burst mode is used.
The longer the burst, the better. The entire 4kB page can be transferred
in < 40 CPU clocks. It takes about 4 CPU clocks to fetch one cache line. Cache is still needed as the memory latency prevents its direct use.

Cache is based in lines as the replacement quantum, because over
fetching has not proven to be valuable in the not so distant past.

For similar reasons, one does not install a cache line of PTEs on
a TLB miss.

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