• Re: Memory ordering (was: Arm ldaxr / stxr loop question)

    From Lawrence D'Oliveiro@21:1/5 to Anton Ertl on Sat Nov 16 21:59:01 2024
    On Fri, 15 Nov 2024 07:25:12 GMT, Anton Ertl wrote:

    @TechReport{adve&gharachorloo95,
    author = {Sarita V. Adve and Kourosh Gharachorloo}, title =
    {Shared Memory Consistency Models: A Tutorial},
    institution = {Digital Western Research Lab},
    year = {1995},
    type = {WRL Research Report},
    number = {95/7},
    ...

    Available online at Bitsavers <http://bitsavers.trailing-edge.com/pdf/dec/tech_reports/WRL-95-7.pdf>
    and mirrors.

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  • From Anton Ertl@21:1/5 to aph@littlepinkcloud.invalid on Fri Nov 15 07:25:12 2024
    aph@littlepinkcloud.invalid writes:
    Yes. That Alpha behaviour was a historic error. No one wants to do
    that again.

    Was it an actual behaviour of any Alpha for public sale, or was it
    just the Alpha specification? I certainly think that Alpha's lack of guarantees in memory ordering is a bad idea, and so is ARM's: "It's
    only 32 pages" <YfxXO.384093$EEm7.56154@fx16.iad>. Seriously?
    Sequential consistency can be specified in one sentence: "The result
    of any execution is the same as if the operations of all the
    processors were executed in some sequential order, and the operations
    of each individual processor appear in this sequence in the order
    specified by its program."

    However, I don't think that the Alpha architects considered the Alpha
    memory ordering to be an error, and probably still don't, just like
    the ARM architects don't consider their memory model to be an error.
    I am pretty sure that no Alpha implementation ever made use of the
    lack of causality in the Alpha memory model, so they could have added
    causality without outlawing existing implementations. That they did
    not indicates that they thought that their memory model was right. An
    advocacy paper for weak memory models [adve&gharachorloo95] came from
    the same place as Alpha, so it's no surprise that Alpha specifies weak consistency.

    @TechReport{adve&gharachorloo95,
    author = {Sarita V. Adve and Kourosh Gharachorloo},
    title = {Shared Memory Consistency Models: A Tutorial},
    institution = {Digital Western Research Lab},
    year = {1995},
    type = {WRL Research Report},
    number = {95/7},
    annote = {Gives an overview of architectural features of
    shared-memory computers such as independent memory
    banks and per-CPU caches, and how they make the (for
    programmers) most natural consistency model hard to
    implement, giving examples of programs that can fail
    with weaker consistency models. It then discusses
    several categories of weaker consistency models and
    actual consistency models in these categories, and
    which ``safety net'' (e.g., memory barrier
    instructions) programmers need to use to work around
    the deficiencies of these models. While the authors
    recognize that programmers find it difficult to use
    these safety nets correctly and efficiently, it
    still advocates weaker consistency models, claiming
    that sequential consistency is too inefficient, by
    outlining an inefficient implementation (which is of
    course no proof that no efficient implementation
    exists). Still the paper is a good introduction to
    the issues involved.}
    }

    - anton
    --
    'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
    Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>

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  • From Michael S@21:1/5 to Anton Ertl on Fri Nov 15 15:22:07 2024
    On Fri, 15 Nov 2024 07:25:12 GMT
    anton@mips.complang.tuwien.ac.at (Anton Ertl) wrote:

    aph@littlepinkcloud.invalid writes:
    Yes. That Alpha behaviour was a historic error. No one wants to do
    that again.

    Was it an actual behaviour of any Alpha for public sale, or was it
    just the Alpha specification? I certainly think that Alpha's lack of guarantees in memory ordering is a bad idea, and so is ARM's: "It's
    only 32 pages" <YfxXO.384093$EEm7.56154@fx16.iad>. Seriously?
    Sequential consistency can be specified in one sentence: "The result
    of any execution is the same as if the operations of all the
    processors were executed in some sequential order, and the operations
    of each individual processor appear in this sequence in the order
    specified by its program."


    Of course, it's not enough for SC.
    What you said holds, for example, for TSO and even by some memory
    ordering models that a weaker than TSO.
    The points of SC is that in addition to that it requires for any two
    stores by different agents to be observed in the same order by all
    agents in the system, including those two.

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  • From Scott Lurndal@21:1/5 to Anton Ertl on Fri Nov 15 14:13:27 2024
    anton@mips.complang.tuwien.ac.at (Anton Ertl) writes: >aph@littlepinkcloud.invalid writes:
    Yes. That Alpha behaviour was a historic error. No one wants to do
    that again.

    Was it an actual behaviour of any Alpha for public sale, or was it
    just the Alpha specification? I certainly think that Alpha's lack of >guarantees in memory ordering is a bad idea, and so is ARM's: "It's
    only 32 pages" <YfxXO.384093$EEm7.56154@fx16.iad>. Seriously?
    Sequential consistency can be specified in one sentence: "The result
    of any execution is the same as if the operations of all the
    processors were executed in some sequential order, and the operations
    of each individual processor appear in this sequence in the order
    specified by its program."

    However, I don't think that the Alpha architects considered the Alpha
    memory ordering to be an error, and probably still don't, just like
    the ARM architects don't consider their memory model to be an error.
    I am pretty sure that no Alpha implementation ever made use of the
    lack of causality in the Alpha memory model, so they could have added >causality without outlawing existing implementations. That they did
    not indicates that they thought that their memory model was right. An >advocacy paper for weak memory models [adve&gharachorloo95] came from
    the same place as Alpha, so it's no surprise that Alpha specifies weak >consistency.

    Perhaps one might ask Dr. Kessler?

    https://acg.cis.upenn.edu/milom/cis501-Fall09/papers/Alpha21264.pdf

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  • From Anton Ertl@21:1/5 to Michael S on Fri Nov 15 17:19:34 2024
    Michael S <already5chosen@yahoo.com> writes:
    On Fri, 15 Nov 2024 07:25:12 GMT
    anton@mips.complang.tuwien.ac.at (Anton Ertl) wrote:

    aph@littlepinkcloud.invalid writes:
    Yes. That Alpha behaviour was a historic error. No one wants to do
    that again.

    Was it an actual behaviour of any Alpha for public sale, or was it
    just the Alpha specification? I certainly think that Alpha's lack of
    guarantees in memory ordering is a bad idea, and so is ARM's: "It's
    only 32 pages" <YfxXO.384093$EEm7.56154@fx16.iad>. Seriously?
    Sequential consistency can be specified in one sentence: "The result
    of any execution is the same as if the operations of all the
    processors were executed in some sequential order, and the operations
    of each individual processor appear in this sequence in the order
    specified by its program."


    Of course, it's not enough for SC.
    What you said holds, for example, for TSO and even by some memory
    ordering models that a weaker than TSO.
    The points of SC is that in addition to that it requires for any two
    stores by different agents to be observed in the same order by all
    agents in the system, including those two.

    That's included in the statement I cited: stores are operations, and
    the behaviour is the same as executing all thoperations in some
    sequential order. I.e., all processors observe everything they
    observe with the same results. I have this definition from <https://en.wikipedia.org/wiki/Sequential_consistency>, which cites
    the following source for it: Leslie Lamport, "How to Make a
    Multiprocessor Computer That Correctly Executes Multiprocess
    Programs", IEEE Trans. Comput. C-28,9 (Sept. 1979), 690-691.

    - anton
    --
    'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
    Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>

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  • From Anton Ertl@21:1/5 to Scott Lurndal on Sat Nov 16 08:58:40 2024
    scott@slp53.sl.home (Scott Lurndal) writes:
    anton@mips.complang.tuwien.ac.at (Anton Ertl) writes:
    Was it an actual behaviour of any Alpha for public sale, or was it
    just the Alpha specification?
    ...
    Perhaps one might ask Dr. Kessler?

    https://acg.cis.upenn.edu/milom/cis501-Fall09/papers/Alpha21264.pdf

    I don't think that anything in the 21264 core would result in the
    Alpha-unique inconsistency; the only core mechanisms that I can think
    of where that would be relevant is value prediction, and the 21264
    does not do that.

    Looking at the memory subsystems of bigger Alpha systems might be more relevant.

    There is a good reason to suspect that the Alpha architects imagined
    hardware that actually did not appear: They did not specify hardware
    byte and 16-bit memory accesses with the justification that a
    first-level write-back cache would require ECC in DEC machines, and
    ECC for bytes (or read-modify-write for keeping ECC on larger units)
    is supposedly too expensive. However, the Alphas without BWX
    instructions (everything up to EV5, but EV56 and later acquired BWX)
    never had a first-level write-back cache.

    And the EV6 which has a first-level write-back cache, implements the
    BWX instructions, so the reasoning against BWX obviously does not hold
    water. Reading on page 31 of the paper above, the 21264 (EV6) uses read-modify-write for updating the ECC data.

    - anton
    --
    'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
    Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>

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